Access control assembly

ABSTRACT

An improved access control assembly including a key assembly constructed to receive a time division binary key code from a remotely located encoder station in the code receive mode of operation, and a lock assembly constructed to control access to a secured device or a secured area, the lock assembly having a predetermined time division binary lock code encoded therein uniquely identifying the lock assembly. When the key assembly is connected to the lock assembly, a time division binary lock recognition code, having a predetermined code format, is generated by the lock assembly and received by the key assembly, the key assembly generating the key code in response to the received lock recognition code detected by the key assembly to have the proper, predetermined code format. The key code generated by the key assembly is received by the lock assembly and compared with the lock code, the lock assembly operating to provide access to the secured device or the secured area in response to a received key code identical to the lock code. The lock assembly generates a signal in response to a comparison indicating the received key code differs from the lock code or in response to the operation of the lock assembly to provide access to the secured device or the secured area which is received by the key assembly and causes the key assembly to destroy the previously received key code and conditions the key assembly in the code receive mode for receiving subsequent key codes from the encoder station.

United St Freeny, Jr.

[21] Appl. No.: 468,486

Related US. Application Data [63] Continuation-in-part of Ser. Nos. 300,098, Oct. 24, 1972, Pat. No. 3,829,833, and Ser. No. 458,330, April 5, 1974.

[52] US. Cl 340/147 MD; 340/164 R [51] Int. Cl. H04Q 9/00; G08B 9/00 [58] Field of Search 340/147 MD, 149 R, 149 A,

[56] References Cited UNITED STATES PATENTS 3,641,316 2/1972 Dcthloff et a1 340/149 A 3,806,874 4/1974 Ehrat 340/149 R 3,848,229 11/1974 Perron et al. 340/149 R Primary Examiner-Donald L. Yusko Attorney, Agent, or FirmDunlap & Codding [57] ABSTRACT An improved access control assembly including a key assembly constructed to receive a time division binary key code from a remotely located encoder station in the code receive mode of operation, and a lock assembly constructed to control access to a secured device or a secured area, the lock assembly having a predetermined time division binary lock code encoded therein uniquely identifying the lock assembly. When the key assembly is connected to the lock assembly, a time division binary lock recognition code, having a predetermined code format, is generated by the lock assembly and received by the key assembly, the key assembly generating the key code in response to the received lock recognition code detected by the key assembly to have the proper, predetermined code for mat. The key code generated by the key assembly is received by the lock assembly and compared with the lock code, the lock assembly operating to provide access to the secured device or the secured area in response to a received key code identical to the lock code. The lock assembly generates a signal in response to a comparison indicating the received key code differs from the lock code or in response to the operation of the lock assembly to provide access to the secured device or the secured area which is received by the key assembly and causes the key assembly to destroy the previously received key code and conditions the key assembly in the code receive mode for receiving subsequent key codes from the encoder station.

38 Claims, 6 Drawing Figures (FA/CODE? 5714 7' ION U.S. Patent Oct. 7,1975 Sheet 1 of 6 3,911,397

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ACCESS CONTROL ASSEMBLY CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of the Applicants co-pending application entitled CODE ELE- MENT IDENTIFICATION METHOD AND APPA RATUS, Ser. No. 300,098, filed Oct, 24, 1972, now U.S. Pat. No. 3,829,833, and the Applicants copending application entitled A COHERENT, FIXED BAUD RATE FSK COMMUNICATION METHOD AND APPARTUS, Ser. No. 458,330 filed Apr. 5, 1974.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to improvements in access control methods and apparatus and, more particularly, but not by way of limitation, to an access control method and apparatus including a lock assembly encoded with a time division binary lock code and a key assembly constructed to receive time division binary key codes from remote locations and to operate the lock assembly when encoded with a key code identical to the lock code.

2. Brief Description of the Prior Art In the past, there have been various mechanical and electronic devices constructed in the nature of a key element and key receiving element wherein the key receiving element received and identified the key element, the key receiving element causing an output indication indicating that the received key element was recognized by the key receiving element for unlocking a door or otherwise enabling or disenabling various devices operated in response to an indication of an identified key element. The key elements and key receiving elements constructed in the past have assumed a variety of physical constructions and modes of operation ranging generally from the typical mechanical type of key element, having one surface shaped to engage and cooperate with tumblers located in the key receiving element, to keys of a card-like or mechanical-like construction, having a plurality of conducting paths or the like oriented and constructed to cooperate with a portion of the key receiving element to establish a type of code via activating the proper electrical circuits in the key receiving element.

The U.S. Pat. No. 3,633,167, issued to Hedin, disclosed a security system utilizing a key-like element, having a plurality of push-buttons connected to a lock control, the push-buttons activating the lock control to provide access to the secured area when actuated in a predetermined sequence. This particular apparatus was also constructed to generate a signal actuating an alarm when the push-buttons were actuated in an improper sequence.

The U.S. Pat. No. 3,651,464, issued to Hedin, disclosed an electrical security system utilizing a key-like element and a key receiving element wherein the key element included a plurality of electrical contacts for conveying a binary coded permutation of electrical signals to the key receiving element when the key element was inserted into the key receiving element establishing electrical contact between the key element electrical contacts and conductor paths of the key receiving element. In an effort to prevent the deciphering of the key element by an unauthorized person, only some of the key element electrical contacts were connected to the key element control circuitry for conveying the code signal to the key receiving element, thereby leaving a number of blank or unused electrical contacts on the key element.

The U.S. Pat. No. 3,544,769, issued to I-Iedin, disclosed an identification key having coded electrical circuits brought into contact with a computer system for verifying various data relating to a credit card transaction wherein the key element contained a control circuit having a plurality of separate circuit paths arranged to correspond to a predetermined binary code identifying the key. In this system, the key was inserted into a key receptacle in such a manner that the encoded data of the key element was transferred to the recognition networks of the key receiving element. The details of the key-card of this system were disclosed in the U.S. Pat. No. 3,336,635, also issued to Hedin. The U.S. Pat. No. Re. 27,013, reissued to Hedin, also disclosed a key-actuated electronic security system having a key element and a key receiving element constructed similar to the key receiving elements of the Hedin patents referred to above.

The U.S. Pat. No. 3,639,906, issued to Tritsch, dis closed a key identification system having a key element insertable into a transmitting apparatus for providing a signal indicative of the code formed in the key element, the signal being received via a code recognition assembly. In this particular apparatus, the key element was formed such that a structural portion thereof engaged a portion of an encoding transmitter and cooperated therewith to cause a signal indicative of the particular code to be transmitted via a transmitter.

The U.S. Pat. No. 3,599,454, issued to Hill, disclosed a mechanical type of key and a key identifier wherein the key included spaced electrical switching elements located thereon to cooperate with a portion of the key identifier assembly for generating a code determined via the on or off position and the sequence of the key element switching devices.

The U.S. Pat. No. 3,668,831, issued to Nicola et aL, disclosed an anti-theft device having a key element containing a plurality of electronic contacts insertable into a lock assembly wherein the electronic contacts of the key element were arranged to provide a code uniquely identifying the particular key element. The electronic contacts of the key element actuated electronic circuitry constructed to identify the code defined via the electronic contacts.

The U.S. Pat. No. 3,628,099, issued to Atkins, disclosed a resistance-responsive control circuit having a discrimination portion and an anti-tampering portion utilized in cooperation with a solenoid-controlled door lock of an automobile. The circuitry was designed such that the door lock of the automobile was actuated via predetermined keying resistances formed on the key element.

The U.S. Pat. No. 3,167,792, issued to Brendemuel, disclosed an electric lock wherein a receptacle included a key way for receiving the key element and a plurality of spaced stationary switch contacts extended into a portion of the key way. The key element included a plurality of switch contacts spaced for engaging the switch contacts of the key receptacle and activating an electronic circuit identifying the key element. The U.S. Pat. No. 2,473,644, issued to Taylor, disclosed an electric locking key device wherein the key element contained a plurality of contact points spaced and positioned thereon to cooperate with contacts located in a key receptacle such that, when the key element was properly positioned in the key operated switch of the key receptacle, the contacts in the key receptacle engaged the contacts of the key element and contacted and activated the key identifying circuit.

The US. Pat. No. 3,518,655, issued to Saul, disclosed a security device wherein the key element had a predetermined electrical resistance and the key receiving apparatus consisted of an unbalanced bridge connected to an alarm, the insertion of a key element having an incorrect or unidentified electrical resistance unbalancing the bridge circuit and activating the alarm.

The US. Pat. No. 3,355,631, issued to Christiansen, disclosed a removable key-actuated control circuit wherein the key element contained spaced inductance elements cooperating with stagger tuned tank circuits of the key receiving and identifying assembly, the insertion of a proper key element causing the tank circuits to resonate at a particular frequency actuating a switching device utilized in cooperation with an electromagnetic locking mechanism.

The Applicants co-pending application entitled CODE ELEMENT IDENTIFICATION METHOD AND APPARATUS, Ser. No. 300,098, filed Oct. 24, 1972, disclosed a code element assembly constructed to receive an interrogate signal from a code identifier assembly when the code element assembly was positioned in a code identifying proximity with the code identifier assembly, the code element assembly emitting a time oriented encoded responder signal in response to the received interrogate signal. The code identifier assembly received and decoded the responder signal and generated a code valid signal in response to an identified code encoded in the received responder signal and a foreign code signal in response to an unidentified code encoded in the received responder signal. The code element assembly was permanently encoded with a time oriented code and the code was not destroyed when the code element assembly was utilized to operate the code identifier assembly. Further, the code identifier assembly was constructed to supply the operating power for the code identifier assembly and the code element. I

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic, schematic view showing an access control assembly constructed in accordance with the present invention.

FIG. 2 is a diagrammatic, schematic view showing one preferred embodiment of the key assembly of the access control assembly of FIG. 1.

FIG. 3 is a diagrammatic, schematic view showing one preferred embodiemnt of the lock assembly of the access control assembly of FIG. 1.

FIG. 4 is a diagrammatic, schematic view showing one embodiment of an encoder station.

FIG. 5 is a diagrammatic, schematic view showing a portion of a modified key assembly for cooperating with the encoder station of FIG. 4.

FIG. 6 is a diagrammatic, schematic view showing a portion of another modified key assembly and a portion of another modified lock assembly.

DESCRIPTION OF THE PREFERRED EMBODIIVIENTS Referring to the drawings in general and to FIG. 1 in particular, shown therein and designated via the general reference numeral 10 is an access control assembly generally comprising: a key assembly 12 and a lock assembly 14. In general, the lock assembly 14 is encoded with a predetermined, time division lock code uniquely identifying the lock assembly 14, and the lock assembly 14 controls access to a secured area. The key assembly 12 has a code receive mode of operation, a code storage mode of operation, and a code transmission mode of operation. In the code receive mode, the key assembly 12 is constructed to receive a predetermined, time division key code generated via a remotely located encoder station 16 and connected to the key assembly 12 by either a direct wire data link 18 or an acoustical data link 20, the received key code being stored in the key assembly 12 in the code storage mode. The access control assembly 10 is constructed such that the key assembly 12 can be connected to the lock assembly 14 and, in this connected position and in the code transmission mode of the key assembly 12, the key assembly 12 sends or transmits the stored key code to the lock assembly 14, the lock assembly 14 being operated to provide access to the secured area when the transmitted key code is identical to the lock code of the lock assembly 14.

It should be particularly noted and emphasized that the terms key and lock have been utilized herein to designate various components and assemblies of the present invention merely for the purpose of clarity and these terms are not to be utilized for the purpose of restricting or, in any manner, limiting the present invention to any particular method and apparatus.

The key assembly 12 generally includes: a key receiver assembly 22, a key code storage unit 24, a data synchronization assembly 26, a key decoder assembly 28 and a key power supply 30. The key power supply 30 is connected to ground via a conductor 32 and a power switch 34 is interposed in the conductor 32, the power switch 34 establishing electrical continuity between the key power supply 30 and ground in a closed position and interrupting electrical continuity between the key power supply 30 and ground in an opened position shown in FIG. 1. The positive side of the key power supply 30 is connected to the key receiver assembly 22, the key code storage unit 24, the data synchronization assembly 26 and the key decoder assembly 28 via a conductor 36, and the key power supply 30 supplies the electrical power for operating the various components and assemblies of the key assembly 12 when in an activated position via the closing of the power switch 34, the key power supply 30 also supplying the electrical power for operating the various components and assemblies of the lock assembly 14 in a manner to be described below. In a preferred form, the key power supply 30 is comprised of one or more battery type of power supplies since the key assembly 12 is preferably constructed to be portable for reasons which will be made apparent below.

The key receiver assembly 22 is constructed to receive the transmitted key code via the direct wire data link 18 connected between the key receiver assembly 22 and the encoder station 16 and also includes a receiver speaker 38 for receiving the transmitted key code via the acoustical data link 20, the receiver speaker 38 converting the received acoustical signals to electrical signals in a manner well known in the art. In any event, the binary coded signals received via the key receiver assembly 22 are converted into a sequence of 5 In the code receive mode, the key code storage unit 24 receives the key code via the signal path 40 and a clock signal generated by the data synchronization assembly 26 and connected to the key code storage unit 24 via the signal path 42. The key code storage unit 24 checks the key code received on the signal path 40 and clocked into the key code storage unit 24 via the clock signal on the signal path 42 to determine if the received key code has a proper, predetermined code format and, if the predetermined code format is detected by the key code storage unit 12, an indicator lamp 44 is illuminated, the indicator lamp 44 being connected to the key code storage unit 24 via a conductor 46. The illumination of the indicator lamp 44 provides a visual, operator-perceivable indication indicating a key code having a predetermined code format has been received and clocked into the key code storage unit 24, and the key code storage unit 24 is constructed to cease accepting key codes connected thereto via the signal path 40 after a key code has been clocked into the key code storage unit 24 having a proper, predetermined code format.

After a key code, having a predetermined code format, has been received and detected by the key code storage unit 24, the key assembly 12 is in the code storage mode wherein the received key code is stored in the key code storage unit 24 and the key code storage unit 24 is conditioned such that subsequent key codes received on the signal path 40 are not clocked into the key code storage unit 24. The key code remains stored in the key code storage unit 24 until the key assembly 12 is conditioned in the code transmission mode.

The key decoder assembly 28 is constructed to receive a predetermined, time division binary lock recognition code via a signal path 48, and a clock signal generated by the data synchronization assembly 26 and connected to the key decoder assembly 28 via a signal path 50. The key decoder assembly 28 includes a portion constructed to detect if the lock recognition code received on the signal path 48 has a proper, predetermined code format, and a signal is generated via the key decoder assembly 28 indicating a proper predetermined code format has been received and detected by the key decoder assembly 28, the signal being connected to the key code storage unit 24 via a signal path 52.

When the key code storage unit 24 receives the signal via the signal path 52 indicating a lock recognition code of a predetermined code format has been re ceived and detected via the key decoder assembly 28 and a clock signal via the signal path 42, the key code storage unit 24 is conditioned in the code transmission mode and the key code stored in the key code storage unit 24 is cyclically generated via the key code storage unit 24, the cyclically generated key code being connected to a signal path 54 for transmission via the key code storage unit 24. The key code storage unit 24 will remain in the code transmission mode cyclically generating the key code stored therein until a signal is received via a signal path 56, the signal on the signal path 56 also being connected to the key decoder assembly 28 causing the signal on the signal path 52 to be changed. The signal on the signal path 56 and the changed signal on the signal path 52 are each received via the key code storage unit 24 causing the key code previously stored in the key code storage unit 24 to be destroyed or cleared and conditioning the key code storage unit 24 in the code receive mode for receiving key codes via the signal path 40.

The data synchronization assembly 26 generates and supplies clock signal pulses on the signal paths 42 and 50 for operating portions of the key code storage unit 24 and the key decoder assembly 28 in a manner generally described before. The data synchronization assembly 26 also provides a clock signal on a signal path 58 for operating portions of the lock assembly 14 and is constructed to receive a signal from the key code storage unit 24 via a signal path 60 for synchronizing the clock signal on the signal path 42 with the incoming, received key code on the signal path 40, in a manner to be described in greater detail below.

The key receiver assembly 22, the key code storage unit 24, the data synchronization nassembly 26, the key decoder assembly 28 and the key power supply 30 are preferably retained in a key housing 62 having a key connector 64 connected to a portion thereof. A plurality of female connectors 68, 70, 72, 74 and 76 are formed on a portion of the key connector 64. As shown in FIG. 1, the signal path 36 is connected to the connector 68, the signal path 48 is connected to the connector 70, the signal path 56 is connected to the connector 72, the signal path 54 is connected to the connector 74, and the signal path 58 is connected to the connector 76.

The key connector 64 is shaped to be inserted into a mating lock connector 78 in a connected position of the key assembly 12 and the lock assembly 14, as shown in FIG. 1. A plurality of spaced male connectors 80, 82, 84, 86 and 88 are formed on the lock connector 78 and, in a connected position of the mating key con nector 64 and the lock connector 78, the male connector 80 is inserted into and connected to the female connector 68, the male'connector 82 is inserted into and connected to the female connector 70, the male connector 84 is inserted into and connected to the female connector 72, the male connector 86 is inserted into and connected to the female connector 74, and the male connector 88 is inserted into and connected to the female connector 76.

The lock connector 64 is formed on a portion of a lock housing 90 and, in one preferred form diagrammatically shown in FIG. 1, the lock housing 90 is constructed to structurally house the various assemblies and components of the lock assembly 14. More particularly, the lock assembly 14 includes: a lock recognition code generator 92, a lock decoder and comparator assembly 94 and a lock control assembly 96, and each of these assemblies is preferably supported within the lock housing 90.

A conductor 98 is connected to the male connector 80 and, in a connected position of the key assembly 12 and the lock assembly 14, the conductor 98 is connected to the signal path 36 via the mating connection between the connectors 68 and 70, thereby connecting the positive side of the key power supply 30 to the conductor 98. The conductor 98 is also connected to the lock recognition code generator 92, the decoder and comparator assembly 94 and the lock control assembly 96. Thus, the key power supply 30 is connected to and provides the electrical power supply for operating the various electrical components and assemblies of the lock assembly 14, in a connected position of the key assembly 12 and the lock assembly 14.

A signal path 100 is connected to the male connector 88 and, in a connected position of the key assembly 12 and the lock assembly 14, the clock signal on the signal path 58 is connected to the signal path 100 via the mating connection between the connectors 76 and 88. The clock signal on the signal path 100 is connected to and received by the lock recognition code generator 92 and the lock decoder and comparator assembly 94. The lock recognition code generator 92 has a predetermined code encoded therein and is constructed to generate the time division binary lock recognition code in response to the received clock signal on the signal path 100, the generated lock recognition code being provided on a signal path 102 and connected to the key decoder assembly 28 via the mating connection between the connectors 82 and 70 connecting the signal paths 102 and 48.

The key code cyclically generated by the key code storage unit 24 and provided on the signal path 54 is connected to the lock decoder and comparator assembly 94 via a signal path 104 and the mating connection between the connectors 74 and 86 connecting the signal paths 54 and 104. The lock decoder and comparator assembly 94 is constructed to receive the key code via the signal path 104 and the clock signal via the signal path 100, the lock decoder and comparator assembly 94 decoding the received key code and comparing the received key code with a predetermined lock code permanently encoded in the lock decoder and comparator assembly 94 uniquely identifying the lock assembly 14. The lock decoder and comparator assembly 94 generates a signal on a signal path 106 which is connected to the signal path 56 via the mating connection between connectors 84 and 72 connecting the signal paths 106 and 56 destroying or clearing the key code stored in the key code storage unit 24 and causing the key decoder assembly 28 to change the signal on the signal path 52, thereby conditioning the key code storage unit 24 in the code receive mode as generally described before.

When the received key code compares identically with the lock code, the lock decoder and comparator assembly 94 generates a signal on a signal path 108 indicating an identical comparison between the key code and the lock code. The lock control assembly 96 is constructed to receive the signal on the signal path 108 indicating an identical comparison between the key code and the lock code and to operate a portion thereof providing access to the secured area, the lock control assembly 96 generating a signal on a signal path 1 l indicating the lock control assembly 96 has been operated to provide access to the secured area. The signal path 110 is connected to the signal path 106, and thus a signal is prooduced on the signal path 56 destroying or clearing the key code stored in the key code storage unit 24 and conditioning the key code storage unit 24 in the code receive mode when the key code received by the lock decoder and comparator assembly 94 compares identically with flue lock code and the lock control assembly 96 has been operated to provide access to the secured area and when the key code received by the lock decoder and comparator assembly 94 does not identically compare with the lock code.

OPERATION OF FIG. 1

The lock assembly 14 controls access to the secured area or device and the key assembly 12 is utilized to gain access to the secured area or device in a controlled manner maintaining the security integrity of the area or device, i.e., access to the secured area or device is gained utilizing the access control assembly 10 only when predetermined conditions exist and the predetermined conditions are determined and set in a manner substantially preventing a violation of the secured area or device in an unauthorized manner or by an unauthorized individual. In various operational embodiments, the lock assembly 14 controls the lock on a security gate of a fenced-in area, or the lock on a door or a window or the like of a manufacturing plant, or the lock on doors of railroad cars, trucks, buildings, shipment containers, for example. In other operational embodiments, the lock assembly 14 controls access to a particular machine such as a data processing machine, for example. In each of these operational embodiments, the key assembly 12 is utilized to operate the lock assembly 14 in a manner providing access to the area or device secured via the lock assembly 14.

For the purpose of illustrating the operation of the present invention, it will be assumed that the lock assembly 14 controls the lock on a truck door and, in this example, the truck door provides access to the secured area (the cargo carrying space of the truck) in an unlocked condition, the truck door securing and preventing access to the secured cargo carrying space in a closed, locked position of the truck door. When the truck is docked at a particular designation, an individual operator desiring to gain entry or access to the secured cargo carrying space must operate the lock assembly 14 to unlock the truck door lock and, to operate the truck door lock controlled via the lock assembly 14, the operator must load the key assembly 12 with a key code which identically corresponds to the lock code of the lock assembly 14.

In this particular operational example, the access control apparatus 10 is utilized to control access to the cargo carrying space of a predetermined number of different trucks and each of the trucks includes a truck door secured by a lock assembly constructed exactly like the lock assembly 14 shown in FIG. 1, except each lock assembly is encoded with a different, predetermined lock code uniquely identifying the particular lock assembly and distinguishing this particular lock assembly from the lock assemblies securing the truck doors of the remaining trucks. Further, in this type of operational embodiment, each truck is identified by a predetermined identification symbol uniquely identifying the particular truck and distinguishing this particular truck from the other trucks and the identification symbol can comprise an alpha-numeric sequence of symbols stamped at a convenient location on the truck. In one form, the identification symbol can be the truck license number; however, since the truck license number changes annually, it is preferred that a different identification symbol be adopted and preferably permanently stamped on the truck or on a portion of the lock assembly at the time the lock assembly is installed. In any event, the identification symbol identifies the particular truck or, more particularly, the particular lock assembly installed on the particular truck and the identification symbol is not the same as the lock code.

To load the key assembly 12 with the desired key code which corresponds identically to the lock code of the lock assembly 14, the operator first obtains the identification symbol uniquely identifying the particular lock assembly 14 which the operator desires to operate. The operator reports this identification symbol to the operator of the encoder station 16 utilizing either an existing two-way radio type of communication system, a teletypewriter type of communication or via a standard, existing telephone communication system,

the operator of the encoder station being a dispatcher of a freight company and the encoder station 16 being located at the headquarters location of the freight company, for example. When the operator reports the identification symbol to the encoder station 16 operator, the operator also requests that the key assembly 12 be loaded with the proper key code corresponding identically to the lock code of the lock assembly 14 desired to be operated. It should be noted that, in one form, the identification symbol is constructed in the form of a time division binary code in a manner allowing the operator to communicate directly with the encoder station 16 and directly enter the identification symbol into the encoder station 16 along with a time division binary request code requestng the encoder station 16 to generate and transmit the key code corresponding identically to the lock code of the lock assembly 14 desired to be operated. In any event, the encoder station 16 is constructed to include a portion having each identification symbol correlated with the key code of the key assembly installed on the particular truck identified by the identification symbol, and the encoder station 16 is constructed to initially determine the key code, the encoder station 16 subsequently generating and transmitting the determined key code identically corresponding to the lock code of the lock assembly 14 uniquely identified by the identification symbol.

The determined key code is transmitted via the encoder station 16 over either the direct wire data link 18 or the acoustical data link 20. To receive the transmitted key code, the key assembly 12 must be conditioned in the code receive mode. Thus, the operator will close the power switch 34 thereby connecting electrical operating power to the key decoder assembly 28, the data synchronization assembly 26, the key code storage unit 24 and the key receiver assembly 22. Since a key code has not yet been entered into the key code storage unit 24, the key code transmitted via the encoder station 16 will be received via the key receiver assembly 22 over the direct wire data link 18 or by the receiver speaker 38 of the key receiver assembly 22 over the acoustical data link 20.

The key code received by the key receiver assembly 22 is received by the key code storage unit 24 over the signal path 40 along with a clock signal generated by the data synchronization assembly 26 and provided on the signal path 42. The key code storage unit 24 determines whether the key code being clocked into the key code storage unit 24 has a proper predetermined code format (a code format representing a valid key code) and, if the key code storage unit 24 detects a key code having a proper predetermined code format has been clocked into the key code storage unit 24, the key code storage unit 24 activates the signal path 46 illuminating the indicator lamp 44 and conditions the key assembly 12 in the code storage mode wherein the received key code remains stored in the key code storage unit 24 and the key code storage unit 24 is conditioned such that subsequently received key codes are not clocked into the key code storage unit 24.

The illumination of the indicator lamp 44 provides an indication perceivable by the operator indicating that a key code, having a predetermined code format, has been received and stored in the key code storage unit 24. The key assembly 12 is now conditioned to be connected to the lock assembly 14 for operating the lock control assembly 96 in a manner providing access to the area secured via the lock assembly 14.

The operator positions the key assembly 12 in a connected position with respect to the lock assembly 14 by inserting the key connector 64 into the lock connector 78 thereby connecting each of the key connectors 68, 70, 72, 74 and 76 to one of the lock connectors 80, 82, 84, 86 and 88, as shown in FIG. 1. In the connected position of the key connector 64 and the lock connector 78, electrical operating power is supplied to the lock code generator 92, the lock decoder and comparator assembly 94 and the lock control assembly 96 by the key power supply 30 via the signal path 36 and the signal path 98 and the mating connection between the connectors 68 and connecting the signal paths 36 and 98, and a clock signal generated via the data synchronization assembly 26 is connected to the lock recognition code generator 92 and the lock decoder and comparator assembly 94 via the signal path 100 and the mating connection between the connectors 76 and 88 connecting the signal paths 58 and 100.

In response to the received clock signal, the lock recognition code generator 92generates a predetermined time division binary lock recognition code which is provided on the signal path 102. The lock recognition code generated by the lock recognition code generator 92 is received by the key decoder assembly 28 on the signal path 48 via the connection between the signal paths 48 and 102 provided via the mating connection between the connectors 70 and 82. If the key decoder assembly 28 detects a lock recognition code, having a predetermined code format, received from the lock recognition code generator 92, the key decoder assembly 28 generates a signal on the signal path 52 indicating a proper lock recognition code having a predetermined code format has been received from the lock assembly 14 connected to the key assembly 12.

When the key code storage unit'24 receives a signal on the signal path 52 indicating a lock recognition code having a predetermined code format has been received from the lock assembly 14 and detected by the key decoder assembly 28, the key code storage unit 24 is conditioned in the code transmission mode and, in the code transmission mode, the key'code storage unit 24 receives a clock signal from the data synchronization assembly 26, the key code storage unit 24 cyclically generating and transmitting the key code stored therein in the code transmission mode. The key code generated by the key code storage unit 24 is provided on the signal path 54 and received by the lock decoder and comparator assembly 94 on the signal path 104 via the mating connection between the connectors 74 and 86 connecting the signal path 54 and 104.

In response to the received key code on the signal path 104 and the received clock signal on the signal path 100, the lock decoder and comparator assembly 94 decodes the received key code and compares the received key code with the predetermined lock code permanently encoded in the lock decoder and comparator assembly 94. If the received key code does not compare identically with the lock code, the lock decoder and comparator assembly 94 generates a signal provided on the signal path 106 and connected to the key decoder assembly 28 and the key code storage unit 24 via the signal path 56 and the mating connection between the connectors 84 and 72 connecting the signal paths 106 and 56 causing the key code stored in the key code storage unit 24 to be destroyed or cleared and the signal on the signal path 52 to be changed via the key decoder assembly 28 conditioning the key code storage unit 24 in the code receive mode. Thus, if the key code does not compare identically with the lock code, the key code stored in the key assembly 12 is automatically destroyed and the operator must again request that the key assembly 12 be loaded with a proper, predetermined key code before the key assembly 12 can be utilized to operate any lock assembly.

If the key code received by the lock decoder and comparator assembly 94 compares identically with the lock code permanently encoded in the lock decoder and comparator assembly 94, the lock decoder and comparator assembly 94 generates a signal on the signal path 108 indicating the lock assembly 14 has received a key code identical to the lock code of the lock assembly 14. The lock control assembly 96 receives the signal on the signal path 108 and operates to unlock the locking device controlled by the lock control assembly 96 or, in the operational example utilized before, the lock control assembly 96 operates to unlock the truck door lock providing access to the secured truck cargo carrying space in response to a received signal on the signal path 108 indicating the received key code compared identically with the lock assembly 14 lock code. Simultaneous with the operating of lock control assembly 96 to unlock the secured device, the lock control assembly 96 generates a signal on the signal path 110 which is received by the key decoder assembly 28 and the key code storage unit 24 via the signal path 56 and the mating connection between the connectors 84 and 72 connecting the signal paths 56 and 110 causing the key code stored in the key code storage unit 24 to be destroyed or cleared and the signal on the signal path 52 to be changed via the key decoder assembly 28 conditioning the key code storage unit 24 in the code receive mode.

The access control assembly provides a means for securing a relatively large number of devices wherein the security of each device is controlled by a lock assembly 14 and each lock assembly 14 is identified by a permanently encoded lock code uniquely identifying each lock assembly 14 and distinguishing each lock assembly 14 from the other lock assemblies 14. Since each of the lock codes is a time division binary code, it is substantially impossible for an unauthorized individual to obtain the lock code for the purpose of violating the security of the access control assembly.

Further, the access control assembly 10 provides a key assembly 12 which can be utilized to operate any of the lock assemblies 14 even though each lock assembly 14 is permanently encoded with a different lock code uniquely identifying each of the lock assemblies 14, since the key assembly 12 is loaded with a predetermined key code via the encoder station 16. The operator of the key assembly 12 does not have access to the particular lock code since the only information required by the operator is the identification symbol. Also, it is not necessary that the operator of the encoder station 16 have access to the various lock codes since the operator need only enter the identification symbol into the encoder station and the key code corresponding to the entered identification symbol is automatically located, generated and transmitted by the encoder station 16. Thus, the access control assembly 10 is constructed in a manner eliminating any necessity of providing the lock codes to the various operators utilizing the system.

Since the key code stored in the key assembly 12 is destroyed when the key code does not compare identically with the lock code and when the lock assembly 14 is operated to provide access to the secured area, the key assembly 12 can only be utilized for a single operation, ie to operate any one of the lock assemblies 14 only one time. In other words, the operator of the key assembly 12 is required to communicate with the encoder station 16 each time it is desired to utilize the key assembly 12 for operating any particular lock assembly.

It should also be emphasized that the key assembly 12 is constructed such that the key assembly 12 must first receive a predetermined lock recognition code from the lock generator 92 of the lock assembly 14 connected to the key assembly 12 prior to the generation and transmission of the key code. In thismanner, any possibility of obtaining the key code by some unau thorized device connected to the key assembly 12 is substantially reduced since it would be necessary for the unauthorized device to first generate a predetermined lock recognition code which is identified by the key assembly 12 before the key assembly 12 will generate and transmit the key code stored therein. In other words, the access control apparatus 10 is constructed such that, after the key assembly 12 is connected to the lock assembly 14, the key assembly 12 must receive and detect the predetermined lock recognition code indicating that the key assembly 12 is connected to a proper lock assembly 14 and then the lock assembly 14 must receive a key code identical to the lock code before the lock assembly 14 will operate to provide access to the secured area or device.

KEY ASSEMBLY Shown in FIG. 2 is one preferred embodiment of the key receiver assembly 22, the key code storage unit 24 and the key decoder assembly 28 of the key assembly 12.

KEY RECEIVER ASSEMBLY The key code is a time division binary code comprising a predetermined number of key code bits, each key code bit having a logic value of one (1) or zero (0) and the key code bits arranged in a predetermined serial arrangement forming the key code. In one preferred form, the encoder station 16 is constructed to generate and transmit the key code via either the direct wire data link 18 or the acoustical data link 20 utilizing the frequency shift key (FSK) method of transmitting time division binary codes wherein a key code bit having a logic value of one (1) is transmitted at one predetermined frequency (f,,,) and a key code bit having a logic value of zero is transmitted at another, distinct frequency (f,). The FSK method for generating and transmitting time division binary codes is well known in the art and one preferred method utilizing FSK is described in detail in the Applicants co-pending application entitled A COI-IERENT, FIXED BAUD RATE FSK COMMUNICATION METHOD AND APPARA- TUS, Ser. No. 458,330 filed Apr. 5, 1974, and referred to before.

The key receiver assembly 22 includes: an amplifier 120 and an FSK demodulator 122. When the key code is transmitted via the acoustical data link 20 the acoustical signal is picked up or received via the speaker 38 and then converted into an electrical signal on a signal path 124 connected between the receiver speaker 38 and the amplifier 120. The amplifier 120 receives the electrical signal on the signal path 124, amplifies the received signal and provides the amplified signal on a signal path 126 connected between the amplifier 120 and the FSK demodulator 122. The amplified signal on the signal path 126 corresponds to the FSK signal transmitted via the encoder station 16 and represents the transmitted key code.

The direct wire data link 18 is connected to the FSK demodulator 122 via the signal path 126 and thus the signal on the signal path 126 corresponds to the transmitted FSK signal representing the key code when transmitted via either the direct wire data link 18 or the acoustical data link 20. In either event, the FSK signal representing the transmitted key code is received by the FSK demodulator 122 on the signal path 126. The FSK demodulator 122 is constructed to sense the frequency of the signal received on the signal path 126 and provide a high output signal on the signal path 40 in response to a received signal having a frequency (f,,,) and a low output signal on the signal path 40 in response to a received signal having a frequency (f,), the FSK demodulator 122 output signal on the signal path 40 being the time division binary coded key code transmitted by the encoder station 16. An FSK demodulator constructed to function in a manner described with respect to the FSK demodulator 122 is commercially available from such companies as Exar Corporation, for example, and one FSK demodulator which has been found to provide satisfactory results is Exar Corporations FSK demodulator designated by the part number XR-ZIO, for example.

KEY DECODER ASSEMBLY The key decoder assembly 28 includes:- a decoder shift register 130, a format decoder 132 and a flip-flop network 134.

The decoder shift register 130 is preferably an N-bit digital shift register of the type generally referred to in the art as a serial in/parallel out type of digital shift register; that is, the binary coded data is clocked into the decoder shift register 130 in a serial manner and binary coded data clocked into the decoder shift register 130 is provided via a predetermined number (P) parallel output signal paths 136 (only the first signal path and last signal path being shown in FIG. 2 and designated therein via the reference numerals 136A and 136B for the purpose of clarity). The decoder shift register 130 receives binary coded data on the signal path 48 and a clock pulse generated by the data synchronization assembly 26 on the signal path 50, the binary coded data being received from the lock recognition code generator 92 and clocked into the decoder shift register 130. A digital shift register constructed to operate in a manner described before with respect to the decoder shift register is commercially available and one such digital shift register is commercially available from Texas Instruments, Inc. and designated by the Texas Instruments, Inc. part number T] No. 74164, for example.

The parallel output signal paths 136 are eachcon nected to the format decoder 132 and the format decoder 132 is constructed to receive the signals on the signal paths 136 representing the binary coded data clocked into the decoder shift register 130, the format decoder 132 providing an output signal in the low state when the received signal on each of the (P) signal paths 136 is in the high state and providing an output signal on a signal path 138 in the high state when any one of the received signals on the (P) signal paths 136 is in the low state. In one preferred form, the format decoder 132 is a NAND gate having a predetermined number of inputs for receiving the signals on the (P) signal paths 136 and providing the single output signal on the signal path 138. One NAND gate which is constructed to operate in a manner described before with respect to the format decoder 132 is commercially available from Texas Instruments, Inc. and designated via the Texas Instruments, Inc. part number TI-7430, for example.

The flip-flop network 134 is constructed to receive the format decoder 132 output signal on the signal path 138 and provide the key decoder assembly 28 output signal on the signal path 52, the flip-flop network 134 providing an output signal on the signal path 52 in the high state in response to a received signal on the signal path 138 in the low state. The flip-flop network 134 output signal on the signal path 52 remains in the high state until the flip-flop network 134 receives a reset signal in the high state on the signal path 56 thereby changing the key decoder assembly 28 output signal on the signal path 52 from the high to the low state. A flipflop network constructed to operate in a manner described before with respect to the flip-flop network 134 is commercially available from Texas Instruments, Inc. and designated via the Texas Instruments, Inc. part number TI-7474, for example.

During the operation of the key decoder assembly 28 and before a lock recognition code has been clocked into the decoder shift register 132, the format decoder 130 output signal on the signal path 138 is in the high state and, in response to a received signal on the signal path 138 in the high state, the flip-flop network 134 output signal remains in the low state, i.e., the flip-flop network 134 is not operated to change the output signal of the flip-flop network 134 in response to a received signal on the signal path 138 in the low state. The key code storage unit 24 is constructed to be conditioned in the code receive mode in response to a received key decoder assembly 28 output signal on the signal path 52 in the low state.

When a lock recognition code is received on the signal path 48 and a clock signal is received on the signal path 50, the lock recognition code on the signal path 48 is clocked into the decoder shift register 130. The predetermined number (P) stages of the decoder shift register 130 are connected to the format decoder 132 via the signals on the predetermined number (P) parallel signal paths 136, and the lock recognition code generated by the lock recognition code generator 92 has a predetermined code format constructed such that the predetermined number (P) stages of the decoder shift register 130 will each produce a signal in the high state on the (P) signal paths 136 when a proper lock recognition code having a predetermined code format has been received from the lock recognition code generator 92 and clocked into the key decoder assembly 28.

When the signals on the (P) signal paths are each in the high state indicating a lock recognition code having a proper, predetermined code format has been received and clocked into the decoder shift register 130, a format decoder 132 output signal in the low state is provided on the signal path 138 causing the operation of the flip-flop network 134 to produce an output signal on the signal path 52 in the high state. The key code storage unit 24 is constructed to be conditioned in the code storage mode or in the code transmission mode in response to a key decoder assembly 28 output signal on the signal path 52 in the high state. In any event, the key code storage unit 24 is constructed such that key codes cannot be received via the signal path 40 until the key decoder assembly 28 output signal on the signal path 52 is changed to the low state.

A reset signal on the signal path 56 in the high state is produced in response to either a determination via the lock decoder and comparator assembly 94 of the lock assembly 14 that the key code transmitted to the lock assembly 14 via the key assembly 12 does not compare with the predetermined lock code of the lock assembly 14 or the operation of the lock control assembly 96 to provide access to the controlled, secured area. In either event, the key decoder assembly 28 output signal on the signal path 52 is changed to the low state and the key code storage unit 24 is constructed to be conditioned in the code receive mode in a manner and for reasons generally described before and to be described in greater detail below with respect to the description of the key code storage unit 24 as shown in FIG. 2.

KEY CODE STORAGE UNIT As mentioned before, the key assembly 12 has three operational modes: the code receive mode, the code storage mode, and the code transmission mode. In the code receive mode, the key code storage unit 24 is constructed to receive an incoming key code on the signal path 40 and to clock the incoming binary code into a key code storage shift register 200. In the code storage mode, the key code storage unit 24 is constructed to retain and store the received key code. In the code transmission mode, the key code storage unit 24 is constructed to cyclically generate and transmit the key code stored in the key code storage shift register 200 until a signal is received from the lock assembly 14 indicating that the lock assembly 14 has been operated to provide access to the secured area or the secured device, or until a signal is received indicating that the key code transmitted to the lock assembly 14 did not compare identically to the lock assembly 14 lock code.

Referring more particularly to the key code storage unit 24 shown in FIG. 2, the signal path 40 from the key receiver assembly 22'is connected to one input of an AND gate 202 and the other input of the AND gate 202 is connected to a signal path 204. The output signal of a flip-flop network 205 is connected to an inverter 206 via a signal path 207 and the output signal of the inverter 206 is provided on the signal path 204 connected to the one input of the AND gate 202. The inverter 206 is constructed to provide an output signal in the high state on the signal path 204 when receiving an input signal in the low state via the signal path 207 and to provide an output signal in the low state on the signal path 204 when receiving an input signal on the signal path 207 in the high state. The AND gate 202 provides an output signal corresponding to the input signal connected thereto via the signal path 40 when the inverter 206 output signal on the signal path 204 is in the high state, and the AND gate 202 provides an output signal in the low state when receiving an inverter 206 output signal on the signal path 204 in the low state.

The AND gate 202 output signal is provided on a signal path connected to one of the inputs of an OR gate 208, the other input of the OR gate 208 being connected to a signal path 212. The OR gate 208 is constructed to provide an output signal on a signal path 214 in the high state when receiving an input signal in the high state on either or both of the signal paths 60 and 212. The output signal of the OR gate 208 on the signal path 214 is connected to the input of the key code storage shift register 200. Thus, in the low state of the signal on the signal path 212, the output signal of the OR gate 208 on the signal path 214 corresponds to the signal on the input signal path 60 or, in other words, corresponds to the incoming binary key code received on the signal path 40 in the high state of the inverter 206 output signal on the signal path 204, for reasons and in a manner to be described in greater detail below.

The key code storage shift register 200 provides the binary key code stored therein in a serial manner on a signal path 54, and thus the code storage shift register 200 provides the key code storage unit 24 output signal on the path 54, the key code storage shift register 200 output signal on the signal path 54 also being connected to one of the inputs of an AND gate 216. The other input of the AND gate 216 is connected to a signal path 218 and the AND gate 216 output signal is provided on the signal path 212 connected to the input of the OR gate 208. An AND gate 220 provides the output signal on the signal path 218, one of the input signals to the AND gate 220 being provided on the signal path 52 and the other input signal to the AND gate 220 being provided via the fip-flop network 205 output signal on the signal path 207. The AND gate 220 is constructed to provide an output signal on the signal path 218 when the input signals connected thereto via the signal paths 52 and 207 are each in the high state.

A clock signal is connected to the key code storage shift register 200 via a signal path 222 and a shift register clock logic network 224, the shift register clock logic network 224 being constructed to provide a shift register clock signal on the signal path 222 in the code receive mode and in the code transmission mode of the key code storage unit 24. The shift register clock logic network 224 includes an AND gate 226 having one input connected to the signal path 42 for receiving the clock signal from the data synchronization assembly 26 and the other input connected to the signal path 52 for receiving the key decoder assembly 28 output signal provided via the flip-flop network 134. The AND gate 226 is constructed to provide an output signal on a signal path 228 corresponding to the clock signal on the signal path 42 in the high state of the signal on the signal path 52 and to provide an output signal in the low state when receiving a signal on the signal path 52 in the low state.

The clock signal on the signal path 42 is also connected to one of the inputs of an AND gate 230 and the other input of the AND gate 230 is connected to the inverter 206 output signal on the signal path 204. The AND gate 230 isconstructed to provide an output signal on a signal path 232 corresponding to the clock signal when receiving an input signal on the signal path 42 in the high state of the signal on the signal path 204 and to provide an output signal in the low state on the signal path 232 when receiving an input signal in the low state on the signal path 204. Thus, in one condition of the shift register clock logic network 224, the clock signal is provided on the signal path 232 and, in one other condition of the shift register clock logic network 224, the clock signal is provided on the signal path 228, for reasons and in a manner to be described in greater detail below.

The AND gate 226 output signal on the signal path 228 is connected to one of the inputs of an AND gate 234 and the other input to the AND gate 234 is connected to the flip-flop network 205 output signal on the signal path 207. The AND gate 234 is constructed to provide an output signal corresponding to the signal on the signal path 228 when receiving an input signal in a high state on the signal path 207 and to provide an output signal in the low state when receiving an input signal in the low state on the signal path 207, the AND gate 234 providing an output signal corresponding to the clock signal received on the signal path 228 is one condition of the shift register clock logic network 224.

The AND gate 234 output signal is connected to one of the inputs of an OR gate 236 via a signal path 238 and the AND gate 230 output signal is connected to the other input of the OR gate 236 via the signal path 232. The OR gate 236 output signal is provided on the signal path 222 connected to the key code storage shift register 200 and the OR gate 236 is constructed to provide an output signal on the signal path 222 in the high state when receiving an input signal in the high state on either the signal path 232 or the signal path 238, the OR gate 236 also providing an output signal in the high state on the signal path 222 when receiving input signals in the high state on the signal paths 232 and 238. The clock signal on the signal path 222 is thus provided via the OR gate 236 output signal.

The key code storage shift register 200 is, more particularly, of the type commonly referred to in the art as a serial in/parallel out type of digital shift register. The binary coded data is clocked into the key code storage shift register 200 in a serial manner and the binary coded data in the key code storage shift register 200 is provided via a predetermined number (M) output signal paths 240 (only the first and the last output signal paths 240 being shown in FIG. 2 and designated therein via the reference numerals 240A and 240B). Serial in/- parallel out type of digital shift registers are commercially available from such manufacturers as Texas Instruments,.lnc., for example, one suitable digital shift register being designated by the Texas Instruments, Inc. part number Tl No. 74164, for example.

The parallel output signal paths 240 from the key code storage shift register 200 are each connected to a code format decoder 242, the format decoder 242 being constructed to provide an output signal on a signal path 244 in the high state when each of the received signals on the signal paths 240 is in the high state and to provide an output signal in the low state on the signal path 244 when any one of the signals on the signal paths 240 is in the low state. The format decoder 242 is constructed and operates in a manner similar to that described before with respect to the format decoder 132.

The format decoder 244 output signal provided on the signal path 244 is connected to the input of the flipflop network 205. The flipflop network 205 provides an output signal in the high state when receiving a signal on the signal path 244 in the high state and the flipflop network 205 output signal is switched to the low state when receiving a signal on the signal path 244 in the low state.

In the binary code receive mode of the key code storage unit 24, the key code storage unit 24 is conditioned to receive a time division binary key code via the signal path 40. In this condition, a key code has not been clocked into the key code storage shift register and the signal on each of the key code storage shift register 200 parallel output signal paths 240 is in the low state, the format decoder 242 output signal on the signal path 244 thus being in the low state.

Since the signal connected to the flip-flop network 205 via the signal path 244 is in the low state, the flipfiop network 205 output signal on the signal path 207 is in the low state. The inverter 206 input signal on the signal path 207 is in the low state and thus the inverter 206 output signal on the signal path 204 is in the high state. Therefore, the AND gate 202 input signal on the signal path 204 is in the high state and the AND gate 202 is conditioned such that the AND gate 202 output signal on the signal path corresponds to the incom ing key code on the signal path 40.

In the code receive mode of the key code storage unit 24, the key assembly 12 has not been connected to the lock assembly 14 and thus the key decoder assembly 28 output signal on the signal path 52 is in the low state, this signal being connected to one of the inputs of the AND gate 220. The input signals connected to the AND gate 220 via the signal paths 52 and 207 are each in the low state, the AND gate 220 providing an output signal on the signal path 218 in the high state in this condition. Since a key code has not been stored in the key code storage shift register 200, the key code stor age shift register 200 output signal on the signal path 54 is in the low state, and thus one of the signals connected to the AND gate 216 on the signal path 218 is in the high state and the other signal connected to the AND gate 216 on the signal path 54 is in the low state, the AND gate 216 providing an output signal on the signal path 212 in the low state in this condition.

The AND gate 216 output signal in the low state is connected to one of the inputs of the OR gate 208 and the OR gate 208 receives a signal corresponding to the incoming, received key code on the signal path 60 connected to the other input of the OR gate 208. Since the signal on the signal path 212 is in the low state and the signal on the signal path 60 corresponds to the incoming, received key code on the signal path 40, the OR gate 208 output signal on the signal path 214 corresponds to the incoming, received key code on the signal path 40, the OR gate 208 output signal being connected to the input of the key code storage shift register 220. The AND gates 200, 216 and 202, the inverter 206 and the OR gate 208 thus cooperate to connect the incoming key code on the signal path 40 to the input of the key code storage shift register 200 in the code receive mode of the key code storage unit 12. The key code on the signal path 214 is clocked into the key code storage shift register 200 via the clock signal on the signal path 222 connected to the key code storage shift register 200 in the code receive mode of the key code storage unit 24, as will be described in greater detail below.

The clock signal is generated via the data synchronization network 26 and the clock signal is connected to the shift register clock logic network 224 via the signal path 42, as described before. Also, the key decoder assembly 28 output signal on the signal path 52 is in the low state in the code receive mode of the key code storage unit 24, and thus the AND gate 226 receiving the key decoder assembly 28 output signal on the signal path 52 in the low states provides an output signal on the signal path 228 in the low state. The AND gate 226 output signal on the signal path 228 and the flip-flop network 205 output signal on the signal path 207 are each connected to the AND gate 234 and the flip-flop network 205 outputsignal on the signal path 207 is in the low state in the code receive mode of the key code storage unit 24, as mentioned before. Thus, the AND gate 234 output signal on the signal path 238 is in the low state in the code receive mode.

The AND gate 230 receives the clock signal on the signal path 42 and the inverter 206 output signal on the signal path 204, the inverter 206 output signal on the signal path 204 being in the high state in the code receive mode. In this condition, the AND gate 230 provides an output signal on the signal path 232 corresponding to the clock signal received on the signal path 42. Since the AND gate 234 output signal on the signal path 238 is in the low state and the AND gate 230 output signal on the signal path 232 corresponds to the clock signal on the signal path 42, the OR gate 236 output signal on the signal path 222 corresponds to the clock signal received on the signal path 232. Thus, in the code receive mode of the key code storage unit 24, the clock signal provided via the data synchronization assembly 26 is connected to the key code storage shift register 200 via the AND gate 230 and the OR gate 236, and the clock signal on the signal path 222 operates to clock the binary key code on the signal path 214 into the key code storage shift register 200.

When a key code having a proper, predetermined code format has been clocked into the key code storage shift register 200, the parallel output signal paths 240 from the key code storage shift register 200 will each be in the high state and the format decoder 242 output signal on the signal path 244 will be switched to the high state causing the flip-flop network 205 to produce an output signal on the signal path 207 in the high state, thereby conditioning the key code storage unit 24 in the code storage mode. In the code storage mode, the inverter 206 output signal on the signal path 204 is in the low state since the flip-flop network 205 output signal on the signal path 207 is in the high state thereby rendering the AND gate 202 inoperative. In the inoperative condition of the AND gate 202, the AND gate 202 output signal on the signal path 60 is in the low state and thus does not correspond to the incoming, received key code on the signal path 40. Further,

the key decoder assembly 28 output signal on the signal path 52 is in the low state in the code storage mode and thus the AND gate 220 output signal on the signal path 218 is in the low state. The key code storage shift register 200 output signal on the signal path 54 is in the low state and thus the AND gate 216 output signal on the signal path 212 is in the low state in the code storage mode of the key code storage unit 24.

The clock signal on the signal path 42 is connected to the AND gates 226 and 230 in the code storage mode of the key assembly 12. However, since the key decoder assembly 28 output signal on the signal path 52 is in the low state, the AND gate 226 output signal on the signal path 228 is in the low state and, since the inverter 206 output signal on the signal path 204 is in the low state, the AND gate 230 output signal on the signal path 232 is in the low state. Thus, the signal on the signal path 222 is in the low state in the code storage mode of the key assembly 12, and the clock signal is not connected to the key code storage shift register 200 for clocking key codes received via the signal path 40 into the key code shift register 200.

The key code storage unit 24 will remain in the code storage mode until the key assembly 12 is connected to the lock assembly 14 and a proper binary coded signal is received from the lock assembly 14, in a manner to be described in greater detail below.

After a key code has been clocked into the key code storage shift register 200 and the format decoder 242 has detected that the key code clocked into the key code storage shift register 200 has a predetermined code format causing the format decoder 242 output signal on the signal path 244 to be switched to the high state thereby causing the flip-flop network 205 to produce an output signal on the signal path 207 in the high state, the key code storage unit 24 can then be positioned in the code transmission mode. In the code transmission mode, the inverter 206 output signal on the signal path 204 is in the low state since the flip-flop network 205 output signal on the signal path 207 is in the high state and thus the AND gate 202 output signal on the signal path is in the low state. Therefore, the AND gate 202 does not function to connect an incoming, received key code on the signal path 40 to the OR gate 208 via the signal path 60 in the code transmission mode.

The clock signal produced by the data synchronization assembly 26 on the signal path 42 is connected to the AND gate 226 and to the AND gate 230 of the shift register clock logic network 224 in the code transmis sion mode. The inverter 206 output signal on the signal path 204 is in the low state and thus the AND gate 230 output signal on the signal path 232 is in the low state. The key decoder assembly 28 produces an output signal on the signal path 52 in response to a proper received lock recognition code from the lock assembly 14 and, in the high state of the key decoder assembly 28 output signal on the signal path 52, the AND gate 226 output signal on the signal path 228 corresponds to the clock signal connected to the AND gate 226 on the signal path 42. The AND gate 226 output signal on the signal path 228 and the flip-flop network 205 output signal on the signal path 207 are each connected to the AND gate 234 and, since the flip-flop network 205 output signal is in the high state in the code transmission mode, the AND gate 234 output signal on the signal path 238 corresponds to the clock signal received on the signal paths 42 and 228. In the code transmission mode, the OR gate 236 receives the clock signal on the signal path 238 and receives a signal in the low state on the signal path 232, the OR gate 236 providing an output signal on the signal path 222 corresponding to the clock signal received on the signal path 42. Thus, in the code transmission mode, the clock signal is connected to the key code storage shift register 200 via the AND gates 226 and 234 and the OR gate 236, the received clock signal on the signal path 222 clocking the key code from the key code storage shift register 200 in a serial manner. The key code clocked from the key code storage shift register 200 is provided on the signal path 54 (the key code storage unit 24 output signal).

The key code storage shift register 200 output signal on the signal path 54 is connected to the input of the AND gate 216 along with the AND gate 220 output signal on the signal path 218. Since the key decoder assembly 28 output signal on the signal path 52 is in the high state and the flip-flop network 205 output signal on the signal path 207 is in the high state in the code transmission mode, the AND gate 220 output signal on the signal path 218 is in the high state. In the high state of the AND gate 220 output signal on the signal path 218, the AND gate 216 output signal on the signal path 212 corresponds to the key code storage shift register 200 output signal on the signal path 54, the AND gate 216 output signal being connected to the OR gate 208 via the signal path 212. The OR gate 208 thus receives a signal in the low state via the signal path 60 and receives the key code storage shift register 200 output signal via the signal path 212, the OR gate 208 providing an output signal on the signal path 214 corresponding to the key code storage shift register 200 output signal on the signal path 54. The OR gate 208 output signal on the signal path 214 is connected to the input of the key code storage shift register 200 and thus the key code clocked from the key code storage shift register 200 in a serial manner is simultaneously clocked back into the key code storage shift register 200 in a serial manner via the AND gate 216, the OR gate 208 and the signal paths 54, 212 and 214. In this manner, the key code previously stored in the key code storage shift register 200 is cyclically clocked from the key code storage shift register 200 and the stored key code is cyclically provided on the key code storage unit 24 output signal 54, the AND gate 216 and the OR gate 208 connecting the last stage of the key code storage shift register 200 to the first stage of the key code storage shift register 200 so that the previously stored key code is cyclically provided via the key code storage shift register output signal on the signal path 54.

The key code stored in the key code storage shift register 200 is cyclically transmitted via the key code storage unit 24 until a reset signal is received on the signal path 56 indicating that the secured area or the secured device has been operated by the lock assembly 14, or that the key code provided on the signal path 54 did not compare identically with the predetermined lock code. In either event, the reset signal on the signal path 56 is switched to the high state resetting the flip-flop network 205, the flip-flop network 205 output signal on the signal path 207 being switched to the low state when receiving a reset signal on the signal path 56 in the high state. Thus, when the reset signal on the signal path 56 is switched to the high state, the flip-flop network 205 is reset causing the flip-flop network 205 output signal on the signal path 207 to be switched to the low state.

The reset signal on the signal path 56 is received via the flip-flop network 134 of the key decoder assembly 28 thereby switching the output signal on the signal path 52 to the low state in a manner described before, and the reset signal on the signal path 56 is also received via the key code storage shift register 200. The key code storage shift register 200 destroys or clears the key code stored therein in response to the received reset signal (all of the shift register stages of the key code storage shift register 200 are returned to a low state), and the key code storage unit 24 is conditioned in the code receive mode in response to the reset signal on the signal path 56 received by the key decoder assembly 28 and the key code storage unit 24.

LOCK ASSEMBLY Shown in FIG. 3 is one preferred embodiment of the lock recognition code generator 92, the lock decoder and comparator assembly 94 and the lock control assembly 96 of the lock assembly 14.

LOCK RECOGNITION CODE GENERATOR The lock recognition code generator 92 includes a code generator 250 and an amplifier 252. The code generator 250 has a predetermined lock recognition code, having a predetermined code format, permanently encoded therein, and is constructed to provide the predetermined, encoded lock recognition code in a serial manner via a code generator 250 output signal on a signal path 254 in response to a received clock signal on the signal path 100 connected to the code generator 250. The code generator 250 output signal on the signal path 254 is connected to the input of the amplifier 252, the amplifier 252 amplifying the received code generator 250 output signal and providing the amplified output signal on the signal path 102 (the amplifier 252 output signal being the lock recognition code generator 92 output signal).

Thus, when the key assembly 12 is connected to the lock assembly 14, the clock signal generated by the data synchronization assembly 26 and provided on the signal path 58 is connected to the code generator 250 via the mating connection between the connectors 76 and 88 and the signal paths 58 and 100. In response to the received clock signal on the signal path 100, the code generator 250 provides the encoded lock recognition code in a serial manner on the signal path 254 which is amplified by the amplifier 252 and provided via the amplifier 252 output signal on the signal path 102. The predetermined lock recognition code generated via the code generator 250 is received by the key decoder assembly 28 in a manner and for reasons described before.

LOCK CONTROL ASSEMBLY The lock control assembly 96 includes: a solenoid 256, having a solenoid plunger 258, a lock pin 260 and a contact arm 262. The solenoid 256 has an energized and a de-energized position and is constructed such that the solenoid plunger 258 is extended a distance from the solenoid 256 in the de-energized position of the solenoid 256 and such that the solenoid plunger 258 is retracted or withdrawn generally toward the solenoid 256 in the energized position of the solenoid. The solenoid 256 is connected to the signal path 108 and the solenoid 256 is energized in response to a received signal on the signal path 108 in the high state.

The lock pin 260 has opposite ends 264 and 266 and a slot 268 is formed in a portion of the lock pin 260 generally between the opposite ends 264 and 266. One end portion of the solenoid plunger 258 is disposed in the slot 268 in the de-energized position of the solenoid 256, the solenoid plunger 258 preventing movement of the lock pin 260 ina locking direction 270 and in an unlocking direction 272.

One end of a compression spring 274 is secured to the end 266 of the lock pin 260 and the opposite end of the compression spring 274 is secured to a support surface 276. The compression spring 274 biases the lock pin 260 in the unlocking direction 272; however, the lock pin 260 is prevented from being moved in the locking direction 272 by the compression spring 258 via the engagement between the solenoid plunger 258 disposed in the slot 268 and the lock pin 260 in the deenergized position of the solenoid 256. The end 264 of the lock pin 260 is connected to a lock mechanism 278 which is constructed to maintain the secured area or the secured device in a locked, secure position in the de-energized position of the solenoid 256 and in the position of the lock pin 260 shown in FIG. 3. The particular construction of the lock mechanism 278 will depend, to some extent, upon the construction and arrangement of the secured area or the secured device. In any event, the lock mechanism 278 is constructed and connected to the lock pin 260 such that the lock mechanism 278 is positioned in a locked position in a de-energized position of the solenoid 258 and such that the movement of the lock pin 260 in the unlocking direction 272 via the compression spring 274 operates to position the lock mechanism 278 in the unlocked position providing access to the secured area or the secured device.

An actuator arm 280 is connected to the lock pin 260 generally between the opposite ends 264 and 266, and the actuator arm 280 is positioned on the lock pin 260 such that the actuator arm 280 is spaced at predetermined distance from the contact arm 262 in the deenergized position of the solenoid 256 wherein the solenoid plunger 258 is disposed in the slot 268 of the lock pin 260. Further, the actuator arm 280 is positioned and oriented on the lock pin 260 such that, in the energized position of the solenoid 256 when the solenoid plunger 258 is removed from the slot 268, the movement of the lock pin 260 in the unlocking direc tion 272 to a position wherein the lock mechanism 278 is positioned in the unlocked position also causes the actuator arm 280 to be moved into contacting engagement with the contact arm 262 moving the contact arm 262 into contacting engagement with a contact 282.

The contact 282 is connected to the key power supply 30 via the signal path 98 in a connected position of the key assembly 12 and the lock assembly 14. The contacting of the contact arm 262 and the contact 282 thus connects the signal path 110 to the key power supply 30 and produces a reset signal on the signal path 110 in the high state.

Assuming the solenoid 256 is de-energized and the lock mechansim 278 is in the locked position, when the key assembly 12 is connected to the lock assembly 14 and the key code compares identically with the lock code, a signal in the high state is produced by the lock decoder and comparator assembly 94 on the signal path 108. The solenoid 256 is energized in response to a received signal in the high state on the signal path 108 causing the solenoid plunger 258 to be removed from the slot 268 in the lock pin 260. When the solenoid plunger 258 is removed from the slot 268, the lock pin 260 is biased in the unlocking direction 272 to a position wherein the lock mechanism is positioned in the unlocked position. As the lock pin 260 is biased in the unlocking direction 272, the actuator arm 280 is simultaneously moved into engagement with the contact arm 262 moving the contact arm 262 into engagement with the contact 282 thereby producing the lock control assembly 96 output signal in the high state on the signal path 110, the signal on the signal path 110 in the high state producing the reset signal connected to the key decoder assembly 28 and the key code storage unit 24 via the signal path 56 in a manner and for reasons described before.

LOCK DECODER AND COMPARATOR ASSEMBLY The lock decoder and comparator assembly 94 generally includes: a lock code generator 284, having the predetermined time division lock code permanently encoded therein, a format detector 286 and a counter 288. In one preferred form, the format detector 286 includes a 4 bit serial in/parallel out type of digital shift register 290 (referred to below as the decoder shift register for the purpose of clarity), such as manufactured by Texas Instruments, Inc., and designated via the Texas Instruments, Inc. part number TI No. 7495A, for example, and a format decoder 292. The key code on the signal path 104 and the clock signal produced on the signal path 100 are each connected to the decoder shift register 290, and the key code is clocked into the decoder shift register 290 in a serial manner in response to the received key code and the received clock signal. Each stage of the decoder shift register 290 is connected to one of the output signal paths 294 (only the first and the last signal paths being shown in FIG. 3 and designated by the reference numerals 294A and 294B for the purpose of clarity), the binary coded data bits of key code clocked into the decoder shift register 290 being provided on the parallel output signal paths 294.

Each of the output signal paths 294 are connected to one of the inputs of the format decoder 292, the format decoder 292 thus receiving the binary coded data bits comprising the key code via the signal paths 294. The

format decoder 292 is constructed to provide an output I signal in the low state on a signal path 296 in response to a received signal in the high state on each of the signal paths 294 indicating a key code having a predetermined code format is being received on the signal path 104.

The counter 288 receives the format decoder 292 output signal on the signal path 296 and is constructed to provide an output signal on the signal path 298 in the high state in response to a received format decoder 292 output signal in the low state. The counter 288 is of the type generally referred to in the art as a two bit counter.

An AND gate 300 receives the counter 288 output signal on the signal path 298 and the clock signal on the signal path 100. When the counter 288 output signal on the signal path 298 is in the high state, the AND gate 300 provides an output signal on a signal path 302 corresponding to the clock signal received on the signal path 100, the AND gate 300 output signal being connected to the lock code generator 284.

The lock code generator 284 has the predetermined lock code permanently encoded therein and is constructed to provide the lock code in a serial manner via the lock code generator output signal on a signal path 304 in response to a received clock signal on the signal path 302. The rate at which the binary coded data bits comprising the lock code are clocked from the lock code generator 284 is synchronized with the binary coded data bits of the key code received by the look assembly 14 on the signal path 104.

An exclusive OR gate 306 receives the key code on the signal path 104 and the lock code on the signal path 304, the exclusive OR gate 306 comparing the received key code and the received lock code and providing an OR gate 306 output signal in the high state on a signal path 308 in response to a difference in the received signals on the signal paths 104 and 304 indicating a differ ence between the received key code and the lock code. The exclusive OR gate 306 thus provides a bit-by-bit comparison of the lock code and the received key code. The exclusive OR gate 306 output signal on the signal path 308 is connected to an inverter 310 which provides an output signal on a signal path 312 in the high state in response to a received signal in the low state-and an output signal on the signal path 312 in the low state in response to a received signal in the high state.

An AND gate 314 receives the inverter 310 output signal on the signal path 312 and the counter 288 output signal on the signal path 298. The AND gate 314 provides an output signal on the signal path 106 in the low state in response to a difference between the signals received on the signal paths 298 and 312 and provides an output signal in the high state in response to identical received signals on the signal paths 298 and 312. Thus, and AND gate 314 output signal on the signal path 106 is in the low state except during that portion of the operation of the key assembly 14 when a received key code is being compared with the lock code and when a received key code differs from the lock code, the AND gate 314 output signal on the signal path 106 being in the high state in either of the two lastmentioned modes of operation.

The AND gate 314 output signal in the high state on the signal path 106 produces the reset signal connected to the key decoder assembly 28 and the key code storage unit 24 via the signal path 56 for reasons described before, the AND gate 314 output signal also being connected to the reset input of the counter 288. The counter 288 is reset in response to a received signal on the signal path 106 in the high state. When each bit of the received key code compares identically with each bit of the lock code, the format detector 286 produces an output signal pulse on the signal path 296 and the counter 288 output signal on the signal path 108 will be switched to the high state energizing the solenoid 256 of the lock control assembly 96, thereby positioning the lock mechanism 278 in the unlocked position and providing access to the secured area or the secured device in a manner described before.

EMBODIMENT OF FIGS. 4 AND 5 Shown in FIG. 4 is one preferred embodiment of the encoder station 16a and shown in FIG. 5 are the modifled portions of the key assembly 12a for receiving the key codes generated and transmitted via the encoder station 16a.

In general, the apparatus shown in FIGS. 4 and 5 provides one preferred system for communicating the time division binary key codes between the encoder station 16a and the key assembly 12a via the direct wire data link 18 or the acoustical data link 20 utilizing frequency shift key (FSK) encoding and decoding techniques wherein a logical zero" is transmitted at one frequency (f,) and a logical one is transmitted at a second, distinct frequency (f,,,), as referred to before with respect to the description of FIG. 2. The key code has a predetermined number (N) of logical ones and logical zeros arranged in a predetermined code format, in this embodiment of the invention. In a preferred form, a synchronization bit" comprising a predetermined logical one or a logical zero is generated and transmitted prior to generation and transmission of the key code and, in a preferred form, the synchronization bit is generated and transmitted twice prior to the generation and transmission of the key code, the synchronization bit being identical to the first message bit in the (N) bit key code for reasons to be described in greater detail below.

The encoder station 16a includes a data entry assembly 416 which is connected to a digital encoder 418 by a predetermined number (N) of parallel data entry sig nal paths 420, the first and the last or (Nth) data entry signal path being specifically shown in FIGS. 1 and 2 and designated therein via the reference numerals 420A and 420B for the purpose of clarity. In one preferred form, the data entry assembly is constructed to permit the predetermined key code bits comprising the key code to be manually entered into the data entry assembly 416 in the predetermined code format (the sequence of ones and zeros comprising the key code) and connected to the digital encoder 418 via the data entry signal paths 420, the data entry assembly 416 comprising thumbwheel switches, push-buttons or other similar decimal-to-binary code converters well known in the art.

The digital encoder 418 generates each key code bit followed by the complement of the previously generated key code bit (referred to sometimes herein as the key code bit complement) for each key code bit of the (N) bit message code, and generates synchronization bits having the same logic level or value as the first key code bit of the key code, in one preferred form. The synchronization bits are generated via the digital encoder 418 prior to the generation of the (N) bit key code. The synchronization bits and the key code bits generated via the digital encoder 418 are connected via a signal path 422 to the control input of an FSK generator 424.

The FSK generator 424 has an off condition and an activated or on condition and generates an output signal having one of two distinct frequencies (f or (f,,,) in response to the received digital encoder 418 output signal, the FSK generator 424 generating an output signal having a frequency (f in response to a received digital encoder 418 output signal having a voltage level representing a logical zero and generating an output signal having a frequency (f,,,) in response to a received digital encoder 418 output signal having a voltage level representing a logical one. 

1. An access control apparatus, comprising: a data synchronization assembly generating an output clock signal; a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising: a key code storage unit having a portion storing a predetermined time division binary key code in the code storage mode, the key code storage unit having a portion for receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly, the lock assembly comprising: a lock decoder and comparator assembly having a portion for receiving the key code clocked from the key code storage unit and for receiving the data synchronization assembly clock signal, the received clock signal clocking the received key code into the lock decoder and comparator assembly, a portion of the lock decoder and comparator assembly having a predetermined time division binary lock code encoded therein, and a portion of the lock decoder and comparator assembly comparing the received key code with the lock code and providing one output signal in response to an identical comparison of the received key code and the lock code and providing the output signal for clearing the key code from the key code storage unit in response to a difference between the compared key code and lock code, the lock decoder and comparator assembly comprising: a decoder shift register receiving the key code from the key code storage unit and the data synchronizatIon assembly clock signal, the received key code being clocked into the decoder shift register via the received clock signal; a lock code generator having the lock code encoded therein and a portion receiving the clock signal generated via the data synchronizaton assembly, the lock code generator providing the lock code via an output signal in response to a received clock signal; means receiving the key code from the key code storage unit and the lock code from the lock code generator, comparing the received lock code and the received key code, and providing the lock decoder and comparator assembly output signal indicating a difference between the lock code and the key code for clearing the key code from the key code storage unit; a format decoder receiving the key code clocked into the decoder shift register and providing an output signal in response to a received key code having a predetermined code format clocked into the decoder shift register; and means receiving the format decoder output signal and the data synchronization assembly clock signal, said means providing the clock signal to the lock code generator in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the decoder shift register.
 2. The apparatus of claim 1 defined further to include: means having a portion for receiving the output signal indicating an identical comparison between the lock code and the key code and receiving the format decoder output signal, said means providing the output signal for clearing the key code stored in the key assembly in response to the received signal indicating an identical comparison between the key code and the lock code and providing the output signal for clearing the key code stored in the key assembly in response to a received key code having a predetermined code format; and wherein the key code storage unit is defined further to include a portion for receiving the lock decoder and comparator assembly output signal indicating an identical comparison between the key code and the lock code and clearing the stored key code in response thereto, and for receiving the lock decoder and comparator output signal indicating a received key code having a predetermined code format and clearing the stored key code in response thereto.
 3. The apparatus of claim 2 wherein the key assembly is defined further to include: a data synchronization assembly generating an output clock signal; and wherein the lock assembly is defined further include: a lock recognition code generator having a predetermined lock recognition code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock recognition code generator providing the lock recognition code via an output signal in response to a received clock signal; and wherein the key assembly is defined further to include: a key decoder assembly receiving the lock recognition code generator output signal and the data synchronization assembly output clock signal, the key decoder assembly providing an output signal for conditioning the key code storage unit in the code transmission mode in response to a received lock recognition code having a predetermined code format; and wherein the key code storage unit includes a portion receiving the key decoder assembly output signal and conditioning the key code storage unit in the code transmission mode in response to a received key decoder output signal indicating a received lock recognition code having a predetermined code format.
 4. An access control apparatus, comprising: a key assembly, comprising: a data synchronization assembly generating an output clock signal; a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assemblY encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising: a key code storage unit, a portion for receiving time division binary key codes and the data synchronization assembly clock signal in a code receive mode and a portion storing one of the received key codes in the code storage mode, the key code storage unit having a portion receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal, and the key code storage unit including a portion receiving a signal for conditioning the key code storage unit in the code receive mode in one state of the received signal and for conditioning the key code storage unit in the code transmission mode in one other state of the received signal, the key code storage unit being conditioned in the code receive mode in response to the received signal in the one state of the received signal and the key code storage unit being conditioned in the code transmission mode in response to the received signal in the one other state of the received signal; a key decoder assembly, comprising: a decoder shift register having a portion for receiving a time division binary lock recognition code and the data synchronization assembly clock signal, the lock recognition code being clocked into the decoder shift register when receiving the data synchronization assembly clock signal and the lock recognition code; a format decoder having a portion for receiving the lock recognition code clocked into the decoder shift register and providing an output signal indicating a lock recognition code having a predetermined code format clocked into the decoder shift register; and means having a portion for receiving the format decoder output signal indicating a lock recognition code having a predetermined code format clocked into the decoder shift register and providing the output signal in the one state for conditioning the key code storage unit in the code transmission mode in response thereto, the key code storage unit receiving the output signal for conditioning the key code storage unit in the code transmission mode and the key code storage unit being conditioned in the code transmission mode in response thereto, said means having a portion for receiving a signal and changing the state of said means output signal to the one other state for conditioning the key code storage unit in the code receive mode in response thereto, the key code storage unit receiving the output signal for conditioning the key code storage unit in the code receive mode in response thereto and the key code storage unit being conditioned in the code receive mode in response thereto; and a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly, the lock assembly comprising: a lock decoder and comparator assembly having a portion for receiving the key code from the key code storage unit and providing an output signal in response to the received key code for clearing the stored key code from the key code storage unit, the lock decoder and comparator output signal being received by the means in the key assembly providing the output sIgnal for conditioning the key code storage unit in the code receive mode in one state of said means output signal and for conditioning the key code storage unit in the code transmission mode in one other state of said means output signal and the state of said means output signal being changed to provide an output signal for conditioning the key code storage unit in the code receive mode in response to receiving the lock decoder and comparator assembly output signal; a lock recognition code generator having a portion storing the predetermined time division binary lock recognition code therein and a portion for receiving the data synchronization assembly clock signal, the lock recognition code being clocked from the lock recognition code generator in response to receiving the data synchronization assembly output signal thereby providing the lock recognition code generator output signal having the lock recognition code encoded therein, the lock recognition code clocked from the lock recognition code generator being received by the decoder shift register in the key assembly.
 5. An access control apparatus, comprising: a data synchronization assembly generating an output clock signal; a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising: a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom; a key code storage unit having a portion for receiving time division binary key codes via the key receiver output signal and for receiving the data synchronization assembly clock signal in a code receive mode of the key code storage unit and storing one of the received key codes in a portion thereof in the code storage mode of the key code storage unit, the key code storage unit receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal, the key code storage unit comprising: a key code storage shift register, having a portion receiving the time division binary key codes and the data synchronization assembly clock signal, the received key codes being clocked into the key code shift register in the code receive mode; means conditioning the key code storage unit in the code storage mode in response to a received key code clocked into the key code storage shift register having a predetermined code format; means conditioning the key code storage unit in the code transmission mode for generating and providing the key code stored in the key code storage unit via the key code storage unit output signal; and means receiving the key codes from the key receiver assembly and the data synchronization assembly clock signal, said means connecting the received key codes and the clock signal to the key code storage shift register and conditioning the key code storage unit in the code receive mode; and a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in respoNse to a key code received from the key assembly, the lock assembly comprising: a lock decoder and comparator assembly having a portion for receiving the key code from the key code storage unit and providing an output signal in response to the received key code for clearing the key code from the key code storage unit, the lock decoder and comparator assembly output signal being received by the key code storage unit and the key code stored in the key code storage unit being cleared from the key code storage unit in response thereto.
 6. An access control apparatus, comprising: a data synchronization assembly generating an output clock signal; a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising: a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom; a key code storage unit having a portion for receiving time division binary key codes via the key receiver assembly output signal and for receiving the data synchronization assembly clock signal in a code receive mode of the key code storage unit and storing one of the received key codes in a portion thereof in the code storage mode of the key code storage unit, the key code storage unit receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal, the key code storage unit comprising: a key code storage shift register having a portion for receiving time division binary key codes and the data synchronization assembly output clock signal, the received key codes being clocked into the key code storage shift register in the code receive mode; a format decoder having a portion for receiving the key code clocked into the key code storage shift register and providing an output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; means having a portion for receiving the format decoder output signal and providing an output signal in the high state in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; an inverter receiving the output signal provided in response to the format decoder output signal and providing an inverted output signal in response thereto, the inverter output signal being in the high state when receiving a signal in the low state and being in the low state when receiving a signal in the high state; an AND gate receiving the inverter output signal and the key codes via the key receiver assembly output signal and providing the received key codes via the AND gate output signal in the high state of the inverter output signal, the AND gate being inoperative in the low state of the inverter output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; and an OR gate receiving the key codes via the AND gate output signal and receiving the key code storage shift register output signal, the OR gate providing the key codes clocked from the key code storage shift register via the OR gate output siGnal in the code transmission mode and providing the key codes provided via the received AND gate output signal via the OR gate output signal in the code receive mode, the OR gate output signal and the data synchronization assembly clock signal being received by the key code shift register, the key codes received by the key receiver assembly being received via the OR gate and provided via the OR gate output signal and clocked into the key code storage shift register in the code receive mode, and the key code clocked from the key code storage shift register being received by the OR gate and provided via the OR gate output signal and clocked back into the key code storage shift register thereby cyclically providing the key code stored in the key code storage shift register via the key code storage shift register output signal in the code transmission mode; and a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly.
 7. The apparatus of claim 6 wherein the key code storage unit is defined further to include: an AND gate receiving the data synchronization assembly output clock signal and the output signal provided in response to the format decoder output signal and providing the received clock signal via the AND gate output signal in the high state of the received output signal provided in response to the format decoder output signal in the code transmission mode; an AND gate receiving the data synchronization assembly output clock signal and the inverter output signal and providing the received clock signal via the AND gate output signal in the high state of the inverter output signal in the code receive mode; and an OR gate receiving the clock signal via the AND gate output signal provided in the code receive mode and providing the clock signal via the OR gate output signal when receiving the clock signal via one of the received output signals from the AND gates, the OR gate output signal being received via the key code storage shift register providing the clock signal in the code transmission mode and the code receive mode.
 8. The apparatus of claim 7 wherein the lock assembly is defined further to include: a lock recognition code generator having a predetermined lock recognition code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock recognition code generator providing the lock recognition code via an output signal in response to a received clock signal; and wherein the key assembly is defined further to include: a key decoder assembly receiving the lock recognition code generator output signal and the data synchronization assembly output clock signal, the key decoder assembly providing an output signal for conditioning the key code storage unit in the code transmission mode in response to a received lock recognition code having a predetermined code format; and wherein the key code storage unit is defined further to include: an AND gate receiving the data synchronization assembly output clock signal and the key decoder assembly output signal and providing the clock signal via the AND gate output signal in a high state of the key decoder output signal indicating a received lock recognition code having a predetermined code format, the clock signal provided via the AND gate output signal in response to a received key decoder assembly output signal in the high state being received via the AND gate providing the clock signal in the code transmission mode.
 9. The apparatus of claim 8 wherein the key code storage unit is defined further to include: an AND gate receiving the output signAl provided in response to the format decoder output signal and the key decoder assembly output signal and providing an output signal in the high state in response to the received key decoder assembly output signal in the high state and the received output signal provided in response to the format decoder output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format; and an AND gate receiving the key code storage shift register output signal and the AND gate output signal provided in response to the received key decoder assembly output signal and the received output signal provided in response to the format decoder output signal, and providing the key code storage shift register via the output signal therefrom when receiving the AND gate output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format, the key code storage shift register output signal provided via the AND gate output signal being received via the OR gate providing the key codes via the OR gate output signal in the code receive mode and in the code transmission mode.
 10. An access control apparatus, comprising: a data synchronization assembly generating an output clock signal; a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising: a key code storage unit having a portion for storing a predetermined time division binary key code in the code storage mode, the key code storage unit having a portion for receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and a key housing structurally supporting the key code storage unit and the data synchronization assembly having a key connector formed on a portion thereof; and a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly, the lock assembly comprising: a lock decoder and comparator assembly having a portion for receiving the key code clocked from the key code storage unit and receiving the data synchronization assembly clock signal, the received clock signal clocking the received key code into the lock decoder and comparator assembly, the lock decoder and comparator assembly having a portion storing a predetermined time division binary lock code therein and a portion comparing the received key code with the lock code and providing one output signal in response to an identical comparison of the received key code and the lock code and providing the output signal for clearing the key code from the key code storage unit in response to a difference between the compared key code and lock code; and a lock housing structurally supporting the lock decoder and comparator assembly having a lOck connector formed on a portion thereof, the lock connector being connectable to the key connector, the key code storage unit output signal being connected to the lock decoder and comparator assembly via the connection between the lock connector and the key connector, the data synchronization assembly output clock signal being connected to the lock decoder and comparator assembly via the connection between the key connector and the lock connector, and the lock decoder and comparator output signal being connected to the key code storage unit via the connection between the key connector and the lock connector.
 11. The apparatus of claim 10 wherein the key assembly includes: a key power supply connected to the key code storage unit and the data synchronization assembly and providing electrical operating power therefor when connected thereto, the key power supply being connected to the lock decoder and comparator assembly and providing the electrical operating power therefor via the connection between the lock connector and the key connector.
 12. An access control apparatus, comprising: a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising: a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom; a key code storage unit having a portion for receiving time division binary key codes via the key receiver output signal and receiving the data synchronization assembly clock signal in a code receive mode and a portion for storing one of the received key codes in a portion thereof in the code storage mode, the key code storage unit receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and a lock assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion for providing an output signal in response to the received key code storage unit output signal, the lock assembly output signal provided in response to receiving the key code storage unit output signal being received by the key code storage unit and the key code stored in the key code storage unit being cleared in response to receiving the lock assembly output signal provided in response to the received key code storage unit output signal.
 13. The apparatus of claim 12 wherein the key receiver assembly is defined further to include: a receiver speaker receiving key codes via an acoustical data link; and means receiving the key codes via a direct wire data link.
 14. An access control apparatus, comprising: a key assembly, comprising: a data synchronization assembly generating an output clock signal; a key code storage unit, having a code receive mode, and a portion for receiving the clock signal generated via the data synchronization assembly, the key code storage unit having a portion for receiving time division binary key codes in the code receive mode, the key code storage unit having a portion for storing one of the received key codes in the code storage mode, and the key code storage unit having a portion for generating an output signal having the keY code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit comprising: a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom; a key code storage shift register receiving the key codes via the key receiver assembly output signal and the data synchronization assembly clock signal and the received key codes being clocked into the key code storage shift register in the code receive mode, at least one of the received key codes being stored in the key code storage shift register in the code storage mode, and the key code storage shift register receiving the data synchronization assembly clock signal and the key code stored in the key code storage shift register being clocked from the key code storage shift register in the code transmission mode; a format decoder having a portion for receiving the key code clocked into the key code storage shift register and providing an output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; means having a portion for receiving the format decoder output signal and providing an output signal in the high state in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; an inverter receiving the output signal provided in response to the format decoder output signal and providing an inverted output signal in response thereto, the inverter output signal being in the high state when receiving a signal in the low state and being in the low state when receiving a signal in the high state; an AND gate receiving the inverter output signal and the key codes via the key receiver assembly output signal and providing the received key codes via the AND gate output signal in the high state of the inverter output signal, the AND gate being inoperative in the low state of the inverter output signal indicating a key code having a predetermined code format clocked into the key storage shift register; and an OR gate receiving the key codes via the AND gate output signal and receiving the key code storage shift register output signal, the OR gate providing the key codes clocked from the key code storage shift register via the OR gate output signal in the code transmission mode and providing the key codes provided via the received AND gate output signal via the OR gate output signal in the code receive mode, the OR gate output signal and the data synchronization assembly clock signal being received by the key code shift register, the key codes received via the key receiver assembly being received via the OR gate and provided via the OR gate output signal and clocked into the key code storage shift register in the code receive mode, and the key code clocked from the key code storage shift register being received via the OR gate and provided via the OR gate output signal and clocked back into the key code storage shift register thereby cyclically providing the key code stored in the key code storage shift register via the key code storage shift register output signal in the code transmission mode; and a lock assembly, comprising: a lock decoder and comparator assembly having a portion for receiving the key code generated via the key assembly in the code transmission mode and providing an output signal in response to a received key code; and a lock control assembly, having a locked position, an unlocked position and a portion receiving the lock decoder and comparator assembly output signal and positioning the lock control assembly in the unlocked position in response thereto.
 15. The apparatus of claim 14 wherein the key code storage unit is defined further to include: an AND gate receiving the data synchronization assembly output clock signal and the output signal pRovided in response to the format decoder output signal and providing the received clock signal via the AND gate output signal in the high state of the received output signal provided in response to the format decoder output signal in the code transmission mode; an AND gate receiving the data synchronization assembly output clock signal and the inverter output signal and providing the received clock signal via the AND gate output signal in the high state of the inverter output signal in the code receive mode; and an OR gate receiving the clock signal via the AND gate output signal provided in the code receive mode and providing the clock signal via the OR gate output signal when receiving the clock signal via one of the received output signals from the AND gates, the OR gate output signal being received via the key code storage shift register providing the clock signal in the code transmission mode and the code receive mode.
 16. The apparatus of claim 15 wherein the lock assembly is defined further to include: a lock recognition code generator having a predetermined lock recognition code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock recognition code generator providing the lock recognition code via an output signal in response to a received clock signal; and wherein the key assembly is defined further to include; a key decoder assembly receiving the lock recognition code generator output signal and the data synchronization assembly output clock signal, the key decoder assembly providing an output signal for conditioning the key code storage unit in the code transmission mode in response to a received lock recognition code having a predetermined code format; and wherein the key code storage unit is defined further to include: an AND gate receiving the data synchronization assembly output clock signal and the key decoder assembly output signal and providing the clock signal via the AND gate output signal in a high state of the key decoder output signal indicating a received lock recognition code having a predetermined code format, the clock signal provided via the AND gate output signal in response to a received key decoder assembly output signal in the high state being received via the AND gate providing the clock signal in the code transmission mode.
 17. The apparatus of claim 16 wherein the key code storage unit is defined further to include: an AND gate receiving the output signal provided in response to the format decoder output signal and the key decoder assembly output signal and providing an output signal in the high state in response to the received key decoder assembly output signal in the high state and the received output signal provided in response to the format decoder output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format; and an AND gate receiving the key code storage shift register output signal and the AND gate output signal provided in response to the received key decoder assembly output signal and the received output signal provided in response to the format decoder output signal, and providing the key code storage shift register via the output signal therefrom when receiving the AND gate output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format, the key code storage shift register output signal provided via the AND gate output signal being received via the OR gate providing the key codes via the OR gate output signal in the code receive mode and in the code transmission mode.
 18. A key apparatus, comprising: a data synchronization assembly generating an output clock signal; a key code stoRage shift register having a portion for receiving time division binary key codes and the data synchronization assembly clock signal and the received key codes being clocked into the key code storage shift register in a code receive mode, a portion of the key code storage shift register storing at least one of the received key codes in a code storage mode, and the key code storage shift register having a portion for receiving the data synchronization assembly clock signal and the key code stored in the key code storage shift register being clocked from the key code storage shift register in a code transmission mode; a key receiver assembly having a portion for receiving time division binary key codes and providing an output signal corresponding to the received key codes, the key receiver assembly output signal being received by the key code storage shift register in the code receive mode of the key code storage shift register; a format decoder connected to the key code storage shift register and receiving the key code clocked into the key code storage shift register and providing an output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; means having a portion for receiving the format decoder output signal and providing an output signal in the high state in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; an inverter receiving the output signal provided in response to the format decoder output signal and providing an inverted output signal in response thereto, the inverter output signal being in the high state when receiving a signal in the low state and being in the low state when receiving a signal in the high state; an AND gate receiving the inverter output signal and the key codes via the key receiver assembly output signal and providing the received key codes via the AND gate output signal in the high state of the inverter output signal, the AND gate being inoperative in the low state of the inverter output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; and an OR gate receiving the key codes via the AND gate output signal and receiving the key code storage shift register output signal, the OR gate providing the key codes clocked from the key code storage shift register via the OR gate output signal in the code transmission mode and providing the key codes provided via the received AND gate output signal via the OR gate output signal in the code receive mode; and wherein the key code storage shift register receives the OR gate output signal and the data synchronization assembly clock signal, the key codes received via the key receiver assembly being received via the OR gate output signal and clocked into the key code storage shift register in the code receive mode, and the key code clocked from the key code storage shift register being received via the OR gate output signal and clocked back into the key code storage shift register thereby cyclically providing the key code stored in the key code storage shift register via the key code storage shift register output signal in the code transmission mode.
 19. The apparatus of claim 18 wherein the key code storage unit is defined further to include an AND gate receiving the data synchronization assembly output clock signal and the output signal provided in response to the format decoder output signal and providing the received clock signal via the AND gate output signal in the high state of the received output signal provided in response to the format decoder output signal in the code transmission mode; an AND gate receiving the data synchronization assembly output clock signal and the inverter output signal and providing the received clock signal via the AND gate output signal in the high state of the inverTer output signal in the code receive mode; and an OR gate receiving the clock signal via the AND gate output signal provided in the code receive mode and providing the clock signal via the OR gate output signal when receiving the clock signal via one of the received output signal from the AND gates, the OR gate output signal being received via the key code storage shift register providing the clock signal in the code transmission mode and the code receive mode.
 20. An access control apparatus, comprising: a key assembly, comprising: means having a portion receiving at least one time division binary key code and a portion providing the received key codes via an output signal therefrom; and a key code storage unit, having a code storage mode, a code receive mode and a code transmission mode, the key code storage unit having a portion for receiving the time division binary key codes from said means providing the key codes via the output signal therefrom in the code receive mode, the key code storage unit having a portion for storing at least one of the key codes received by the key code storage unit in the code storage mode, and the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and a lock assembly having a portion for receiving the key code storage unit output signal having the key code stored in the key code storage unit encoded therein and a portion for providing an output signal for clearing the key code stored in the key code storage unit in response to the lock assembly receiving the key code storage unit output signal, the lock assembly output signal for clearing the key code from the key code storage unit being received by the key code storage unit and the key code stored in the key code storage unit being cleared from the key code storage unit in response to the received clock assembly output signal for clearing the key code.
 21. The apparatus of claim 20 wherein the lock assembly is defined further to include: a lock decoder and comparator assembly having a portion for receiving the key code from the key code storage unit and providing an output signal in response to receiving the key code for clearing the key code from the key code storage unit, the lock decoder and comparator output signal being received via the key code storage unit and the key code stored in the key code storage unit being cleared in response to the received lock decoder and comparator assembly output signal.
 22. The apparatus of claim 21 defined further to include: a data synchronization assembly generating an output clock signal; and wherein the key code storage unit includes a portion receiving the clock signal for clocking the key code stored in the key code storage unit from the key code storage unit in the code transmission mode.
 23. The apparatus of claim 22 wherein the lock decoder and comparator assembly includes a portion receiving the clock signal generated via the data synchronization assembly for clocking the key code into a portion of the lock decoder and comparator assembly, the lock decoder and comparator assembly having a predetermined lock code encoded therein and a portion comparing the received key code with the lock code and providing one output signal in response to an identical comparison of the key code and the lock code and providing the output signal for clearing the key code from the key code storage unit in response to a difference between the compared key code and lock code.
 24. The apparatus of claim 23 wherein the lock assembly is defined further to include: a lock control assembly, having a locked position, an unlocked position, and a portion receiving the lock decoder and comparator assembly outPut signal provided in response to an identical comparison of the key code and the lock code, the lock control assembly being positioned in the unlocked position in response to a received lock decoder and comparator assembly output signal indicating an identical comparison between the key code and the lock code.
 25. The apparatus of claim 24 wherein the lock control assembly is defined further to include a portion providing an output signal in response to the positioning of the lock control assembly in the unlocked position; and wherein the key code storage unit is defined further to include a portion receiving the lock control assembly output signal indicating the positioning of the lock control assembly in the unlocked position and clearing the key code from the key code storage unit in response thereto.
 26. The apparatus of claim 25 wherein the lock control assembly is defined further to include: a lock mechanism having a locked and an unlocked position; a lock pin connected to the lock mechanism movable in a locking direction to a position positioning the lock mechanism in the locked position, and movable in an unlocking direction to a position positioning the lock mechanism in the unlocked position; means connected to the lock pin biasing the lock pin in the unlocking direction; means having a portion removably connected to the lock pin and another portion receiving the lock decoder and comparator output signal indicating an identical comparison between the lock code and the key code, said means preventing movement of the lock pin in the unlocking direction when connected to the lock pin, the lock pin being biased in the unlocking direction positioning the lock mechanism in the unlocked position upon the removal of the portion of said means removably connected to the lock pin in response to the lock decoder and comparator output signal indicating an identical comparison between the key code and the lock code; and means having a portion engageable with a portion of the lock pin in one position of the lock pin, said means providing the output signal indicating the positioning of the lock control assembly in the unlocked position in the position of the lock pin positioning the lock mechanism in the unlocked position.
 27. The apparatus of claim 23 wherein the lock decoder and comparator assembly is defined further to include: a lock code generator having the lock code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock code generator providing the lock code via an output signal in response to a received clock signal; and means receiving the key code and the lock code generator output signal, comparing the key code and the lock code, and providing the lock decoder and comparator assembly output signal indicating a difference between the lock code and the key code.
 28. A key assembly, comprising: a data synchronization assembly generating an output clock signal; a key receiver assembly having a portion receiving time division binary key codes and providing the received key codes via a key receiver assembly output signal; a key code storage shift register having a portion receiving time division binary key codes via the key receiver assembly output signal and the data synchronization assembly clock signal, the received key codes being clocked into the key code storage shift register in a code receive mode, the key code storage shift register having a portion storing at least one of the received key codes in a code storage mode, and the key code storage shift register having a portion for receiving the data synchronization assembly clock signal and clocking the key code stored in the key code storage shift register from the key code storage shift register in a code transmission mode.
 29. The apparatus of claim 28 wherein the key receiver assembly is defined further to include: a receiver speaker receiving key codes via an acoustIcal data link; and means receiving the key codes via a direct wire data link.
 30. An access control assembly, comprising: a key assembly, comprising: a key receiver assembly receiving time division binary key codes and providing an output signal corresponding to the received key codes; a key code storage unit, having a code storage mode, a code receive mode, and a code transmission mode, the key code storage unit having a portion for receiving the key codes via the key receiver assembly output signal in the code receive mode, the key code storage unit having a portion storing at least one of the key codes received by the key code storage unit in the code storage mode, and the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode; and a lock assembly, comprising: a lock decoder and comparator assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion providing an output signal in response to the lock decoder and comparator assembly receiving a key code storage unit output signal having encoded therein a key code; and a lock control assembly having a locked position and an unlocked position, the lock control assembly having a portion for receiving the lock decoder and comparator assembly output signal and positioning the lock control assembly in the unlocked position in response to a received lock decoder and comparator assembly output signal.
 31. An access control assembly, comprising: a data synchronization assembly generating and providing a clock signal; a key assembly, comprising: a key decoder assembly having a portion for receiving a predetermined time division binary lock recognition code, the key decoder assembly having a portion for providing an output signal in response to the key decoder assembly receiving a lock recognition code having a predetermined code format; and a key code storage unit having a code transmission mode and a portion for storing a predetermined time division binary key code, the key code storage unit having a portion for receiving the key decoder assembly output signal and conditioning the key code storage unit in the code transmission mode in response to receiving the key decoder assembly output signal, the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in response to receiving the key decoder assembly output signal; and a lock assembly, comprising: a lock recognition code generator having a portion storing a predetermined time division binary lock recognition code, and a portion providing an output signal having the lock recognition code encoded therein, the lock recognition code provided via the lock recognition code generator output signal being received by the key decoder assembly; and a lock decoder and comparator assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion providing an output signal in response to the lock decoder and comparator assembly receiving a key code storage unit output signal having encoded therein a key code having a predetermined code format.
 32. An access control assembly, comprising: a data synchronization assembly generating and providing a clock signal; a key assembly, comprising: a key decoder assembly having a portion for receiving a predetermined time division binary lock recognition code, the key decoder assembly having a portion for providing an output signal in response to the key decoder assembly receiving a lock recognition code having a predetermined code format; and a key code storage unit having a code transmission mode and a portion for storing a predetermined time division binary key code, the key code storage unit having a portion for receiVing the key decoder assembly output signal and conditioning the key code storage unit in the code transmission mode in response to receiving the key decoder assembly output signal, the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in response to receiving the key decoder assembly output signal; and a lock assembly, comprising: a lock recognition code generator having a portion storing a predetermined time division binary lock recognition code, and a portion providing an output signal having the lock recognition code encoded therein, the lock recognition code provided via the lock recognition code generator output signal being received by the key decoder assembly; and a lock decoder and comparator assembly having a portion storing a predetermined time division binary lock code, the lock decoder and comparator assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion for comparing the received key code encoded in the key code storage unit output signal with the lock code stored in the lock decoder and comparator assembly and providing an output signal in response to an identical comparison of the lock code and the key code.
 33. A method for operating lock assembly utilizing a key assembly adapted to receive time division binary key codes, the lock assembly having a time division binary lock code uniquely identifying the lock assembly, comprising the steps of: conditioning the key assembly in a code receive mode for receiving time division binary key codes; receiving the time division binary key codes via the key assembly; conditioning the key assembly in a code storage mode for storing one of the receiving key codes; storing one of the received key codes in the key assembly; conditioning the key assembly in the code transmission mode for providing a signal having the key code stored in the key assembly encoded therein; generating a signal having the key code stored in the key assembly encoded therein, the signal having the key code encoded therein being provided via the key assembly; receiving the signal from the key assembly having the key code encoded therein via the lock assembly; comparing the received key code with the lock code uniquely identifying the lock assembly; generating a signal indicating a difference between the received key code and the lock code; receiving via the key assembly the signal from the lock assembly indicating a difference between the key code and the lock code; and clearing the key code stored in the key assembly from the key assembly in response to receiving the signal indicating a difference between the key code and the lock code.
 34. A method for operating a lock mechanism having a locked position and an unlocked position wherein the lock mechanism is controlled via a lock assembly utilizing the key assembly adapted to receive time division binary key codes, the lock assembly having a time division binary lock code uniquely identifying the lock assembly, comprising the steps of: conditioning the key assembly in a code receive mode for receiving the time division binary key codes; receiving the time division binary key codes via the key assembly; conditioning the key assembly in a code storage mode for storing one of the received key codes; storing one of the received key codes in the key assembly; conditioning the key assembly in a code transmission mode for providing a signal having the key code stored in the key assembly encoded therein; generating a signal having the key code stored in the key assembly encoded therein, the signal having the key code encoded therein being provided via the key assembly; receiving the signal from the key assembly having the key code encoded therein via the lock assembly; comparing the received key code with the lock Code uniquely identifying the lock assembly; generating a signal indicating an identical comparison between the received key code and the lock code; unlocking the lock mechanism in response to the signal indicating an identical comparison between the lock code and the key code; generating a signal indicating the unlocked status of the lock mechanism via the lock assembly; receiving the signal indicating the unlocked status of the lock mechanism via the key assembly; and clearing the key code stored in the key assembly from the key assembly in response to the received signal indicating the unlocked status of the lock mechanism.
 35. A method for operating a lock mechanism having a locked position and an unlocked position wherein the lock mechanism is controlled by a lock assembly, having a time division binary lock code uniquely identifying the lock assembly, utilizing a key assembly adapted to receive time division binary key codes, comprising the steps of: conditioning the key assembly in a code receive mode for receiving time division binary key codes; receiving time division binary key codes via the key assembly; conditioning the key assembly in a code storage mode for storing one of the received key codes; storing one of the received key codes in the key assembly; conditioning the key assembly in a code transmission mode for providing a signal having the key code stored in the key assembly encoded therein; generating a signal having the key code stored in the key assembly encoded therein, the signal having the key code encoded therein being provided via the key assembly; receiving the signal from the key assembly having the key code encoded therein via the lock assembly; comparing the received key code with the lock code uniquely identifying the lock assembly; generating a signal indicating an identical comparison between the received key code and the lock code; generating a signal indicating a difference between the compared key code and lock code; unlocking the lock mechanism in response to the signal indicating an identical comparison between the lock code and the received key code; generating a signal indicating the unlocked status of the lock mechanism; receiving via the key assembly the signal from the lock assembly indicating a difference between the lock code and the key code and receiving via the key assembly the signal from the lock assembly indicating the unlocked status of the lock mechanism; and clearing the key code stored in the key assembly from the key assembly in response to the received signal indicating a difference between the lock code and the key code and clearing the key code stored in the key assembly from the key assembly in response to the received signal indicating the unlocked status of the lock mechanism.
 36. A method for operating a lock mechanism having a locked position and an unlocked position wherein the lock mechanism is controlled by a lock assembly utilizing a key assembly having a time division binary key code encoded therein, the lock assembly having a time division binary lock code uniquely identifying the lock assembly and a time division binary lock recognition code having a predetermined code format, comprising the steps of: generating a signal having the predetermined time division binary lock recognition code encoded therein via the lock assembly, the lock recognition code having a predetermined code format; receiving the signal having the lock recognition code encoded therein via the key assembly; generating a signal, having the time division binary key code encoded therein, via the key assembly in response to a received signal encoded with the lock recognition code having the predetermined code format; receiving the signal from the key assembly encoded with the key code via the lock assembly; comparing the received key code with the predetermined time division binary lock code; generating a siGnal in response to an identical comparison between the received key code and the lock code; and unlocking the lock mechanism in response to the signal indicating an identical comparison between the key code and the lock code.
 37. The method of claim 36 defined further to include the steps of: generating a signal indicating the unlocked status of the lock mechanism via the lock assembly; receiving the signal indicating the unlocked status of the lock mechanism via the key assembly; and clearing the key code from the key assembly in response to a received signal indicating the unlocked status of the lock mechanism.
 38. The method of claim 37 defined further to include the steps of: generating a signal in response to a difference between the compared key code and lock code via the lock assembly; receiving the signal indicating a difference between the compared key code and lock code via the key assembly; and clearing the key code from the key assembly in response to the received signal indicating a difference between the compared lock code and key code. 